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8Gb/s capacitive low power and high speed 4-PWAM transceiver design

Published:16 May 2010Publication History

ABSTRACT

In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other works. A novel technique is proposed to reduce power and to increase speed by using capacitive driven low swing transceiver. The proposed design saves 1.74~2.4x power and 4x higher data rate than conventional designs. To implement 4-PWAM transmitter new phase controller and adaptive capacitance network are designed. At receiver side, new architectures for PWM and PAM demodulation are proposed.

References

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          cover image ACM Conferences
          GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI
          May 2010
          502 pages
          ISBN:9781450300124
          DOI:10.1145/1785481

          Copyright © 2010 ACM

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          Publication History

          • Published: 16 May 2010

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