ABSTRACT
Modern multi-processor systems need to provide guaranteed services to their users. A communication assist (CA) helps in achieving tight timing guarantees. In this paper, we present a CA for a tile-based MP-SoC. Our CA has smaller memory requirements and a lower latency than existing CAs. The CA has been implemented in hardware. We compare it with two existing DMA controllers. When compared with these DMAs, our CA is up-to 44% smaller in terms of equivalent gate count.
- ARM. Arm primecell™ DMA controller, http://www.arm.com/armtech/PrimeCell?OpenDocument.Google Scholar
- Culler, D., et al. Parallel computer architecture: a hardware/software approach. Morgan Kaufmann Publishers, Inc. Google ScholarDigital Library
- Dave, C., and Charles, F. A scalable high-performance DMA architecture for DSP applications. In ICCD '00:,p. 414. Google ScholarDigital Library
- Moonen, A., et al. A multi-core architecture for in-car digital entertainment. In Proc. of GSPx Conference (2005).Google Scholar
- Niewland, et al. The impact of higher communication layers on NOC supported MP-SoCs. In NOCS '07 (2007), pp. 107--116. Google ScholarDigital Library
- Nikolov, H., et al. Multi-processor system design with ESPAM. In Proc. of CODES+ISSS (06),pp. 211--216. Google ScholarDigital Library
- Sang-Il, H., et al. An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. In DAC '04 , pp. 250--255. Google ScholarDigital Library
Index Terms
- A predictable communication assist
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