ABSTRACT
Phase Change Memory (PCM) is emerging as a scalable and power efficient technology to architect future main memory systems. The scalability of PCM is enhanced by the property that PCM devices can store multiple bits per cell. While such Multi-Level Cell (MLC) devices can offer high density, this benefit comes at the expense of increased read latency, which can cause significant performance degradation. This paper proposes Morphable Memory System (MMS), a robust architecture for efficiently incorporating MLC PCM devices in main memory. MMS is based on observation that memory requirement varies between workloads, and systems are typically over-provisioned in terms of memory capacity. So, during a phase of low memory usage, some of the MLC devices can be operated at fewer bits per cell to obtain lower latency. When the workload requires full memory capacity, these devices can be restored to high density MLC operation to have full main-memory capacity. We provide the runtime monitors, the hardware-OS interface, and the detailed mechanism for implementing MMS. Our evaluations on an 8-core 8GB MLC PCM-based system show that MMS provides, on average, low latency access for 95% of all memory requests, thereby improving overall system performance by 40%.
- International Technology Roadmap for Semiconductors, ITRS 2008 Update. http://www.itrs.net/Links/2008ITRS/Home2008.htm.Google Scholar
- B. Abali et al. Hardware compressed main memory: Operating system support and performance evaluation. IEEE Trans. Comput., 50(11):1219--1233, 2001. Google ScholarDigital Library
- Analog Devices Inc. Data Conversion Handbook.Google Scholar
- F. Bedeschi et al. A bipolar-selected phase change memory featuring multi-level cell storage. IEEE Journal of Solid-State Circuits, 44(1):217--227, 2009.Google ScholarCross Ref
- T. Cho et al. A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes. IEEE Journal of Solid-State Circuits, 36(11), 2001.Google Scholar
- L. Kevin et al. Disaggregated memory for expansion and sharing in blade servers. In ISCA-36, pages 267--278, 2009.Google Scholar
- T. Kgil, D. Roberts, and T. Mudge. Improving nand flash based disk caches. In ISCA-35, 2008. Google ScholarDigital Library
- B. Lee et al. Architecting Phase Change Memory as a Scalable DRAM Alternative. In ISCA-36, 2009. Google ScholarDigital Library
- S. Lee et al. FlexFS: A Flexible Flash File System for MLC NAND Flash Memory. In USENIX '09, 2009. Google ScholarDigital Library
- J. Lin et al. Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems. In HPCA-14, 2008.Google Scholar
- K. Luo et al. Balancing throughput and fairness in SMT processors. In ISPASS-2001.Google Scholar
- R. L. Mattson et al. Evaluation techniques in storage hierarchies. IBM Journal of Research and Development, 9(2):78--117, 1970. Google ScholarDigital Library
- T. Nirschl et al. Write strategies for 2 and 4-bit multi-level phase-change memory. In Proceedings of the IEEE International Electron Devices Meeting, 2007.Google ScholarCross Ref
- M. Qureshi et al. Scalable high performance main memory system using phase-change memory technology. In ISCA-36, 2009. Google ScholarDigital Library
- M. K. Qureshi et al. Improving read performance of phase change memories via write cancellation and write pausing. In HPCA-16, 2010.Google ScholarCross Ref
- M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In MICRO-39, 2006. Google ScholarDigital Library
- S. Raoux et al. Phase-change random access memory: A scalable technology. IBM Journal of R. and D., 52(4/5):465--479, 2008. Google ScholarDigital Library
- B. Razavi. Principles of data conversion system design. Wiley-IEEE Press., New York, 1995.Google Scholar
- A. Snavely, D. M. Tullsen, and G. Voelker. Symbiotic jobscheduling with priorities for a simultaneous multithreading processor. In SIGMETRICS-2002. Google ScholarDigital Library
- The Standard Performance Evaluation Corporation. Requirements of SPEC CPU 2006. http://www.spec.org/cpu2006/Docs/system-requirements.html.Google Scholar
- G. E. Suh et al. A new memory monitoring scheme for memory-aware scheduling and partitioning. In HPCA-8, 2002. Google ScholarDigital Library
- J. Thatcher et al. Nand flash solid state storage for the enterprise: An in-depth look at reliability. Solid State Storage Initiative (SNIA), 2009.Google Scholar
- C. A. Waldspurger. Memory resource management in VMware ESX server. SIGOPS Oper. Syst. Rev., 36(SI):181--194, 2002. Google ScholarDigital Library
- P. Zhou et al. Dynamic tracking of page miss ratio curve for memory management. In ASPLOS-XI, 2004. Google ScholarDigital Library
- P. Zhou, B. Zhao, J. Yang, and Y. Zhang. A durable and energy efficient main memory using phase change memory technology. In ISCA-36, 2009. Google ScholarDigital Library
Index Terms
- Morphable memory system: a robust architecture for exploiting multi-level phase change memories
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