Subhasish Mitra
ABSTRACT
Post-silicon validation is used to detect and fix bugs in integrated circuits and systems after manufacture. Due to sheer design complexity, it is nearly impossible to detect and fix all bugs before manufacture. Post-silicon validation is a major challenge for future systems. Today, it is largely viewed as an art with very few systematic solutions. As a result, post-silicon validation is an emerging research topic with several exciting opportunities for major innovations in electronic design automation. In this paper, we provide an overview of the post-silicon validation problem and how it differs from traditional pre-silicon verification and manufacturing testing. We also discuss major post-silicon validation challenges and recent advances.
- {Abramovici 06} Abramovici, M., P. Bradley, K. N. Dwarakanath, P. Levin, G. Memmi and D. Miller, "A Reconfigurable Design-for-Debug Infrastructure for SoCs," Proc. Design Automation Conf., pp. 7--12, 2006. Google Scholar
Digital Library
- {Anis 07} Anis, E., and N. Nicolici, "On Using Lossless Compression of Debug Data in Embedded Logic Analysis," Proc. Intl. Test Conf., 2007.Google Scholar
- {Anis 08} Anis E., and N. Nicolici, "On By-passing Blocking Bugs during Post-silicon Validation," Proc. European Test Symp., pp. 69--74, 2008. Google ScholarDigital Library
- {Bardell 87} Bardell, P. H., W. H. McAnney and J. Savir, Built-In Test for VLSI: Pseudo-random Techniques, John Wiley & Sons, 1987. Google ScholarDigital Library
- {Barrett 09} Barrett, C., R. Sebastiani, S. A. Seshia, and C. Tinelli, "Satisfiability Modulo Theories," Handbook of Satisfiability, IOS Press, 2009.Google Scholar
- {Bayazit 05} Bayazit, A. A., and S. Malik, "Complementary Use of Runtime Validation and Model Checking," Proc. Intl. Conf. CAD, pp. 1052--1059, 2005. Google ScholarDigital Library
- {Boule 05} Boule, M., and Z. Zilic, "Incorporating Efficient Assertion Checkers into Hardware Emulation," Proc. Intl. Conf. Computer Design, pp. 221--228, 2005. Google ScholarDigital Library
- {Brayton 10} Brayton, R. K., et al., Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification. http://www.eecs.berkeley.edu/~alanmi/abc/Google Scholar
- {Bryant 86} Bryant, R. E., "Graph-based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, Vol. C-35, No. 8, pp. 677--691, Aug. 1986. Google ScholarDigital Library
- {Caty 05} Caty, O., P. Dahlgren and I. Bayraktaroglu, "Microprocessor Silicon Debug Based on Failure Propagation Tracing," Proc. Intl. Test Conf., pp. 293--302, 2005.Google Scholar
- {Chang 08} Chang, K. H., I. L. Markov and V. Bertacco, "Automating Post-silicon Debugging and Repair," IEEE Computer, Vol. 41, No. 7, pp. 47--54, July 2008. Google ScholarDigital Library
- {Clarke 00} Clarke, E. M., O. Grumberg and D. Peled, Model Checking, MIT Press, 2000.Google ScholarDigital Library
- {Dahlgren 03} Dahlgren, P., P. Dickinson and I. Parulkar, "Latch Divergency in Microprocessor Failure Analysis in Microprocessor Failure Analysis," Proc. Intl. Test Conf., pp. 755--763, 2003.Google Scholar
- {de Paula 08} de Paula, F. M., M. Gort, A. J. Hu, S. E. Wilton and J. Yang, "BackSpace: Formal Analysis for Post-Silicon Debug," Proc. Intl. Conf. Formal Methods in CAD, 2008. Google ScholarDigital Library
- {Eichelberger 77} Eichelberger, E. B., and T. W. Williams, "A Logic Design Structure for LSI Testability," Proc. Design Automation Conf., pp. 462--468, 1977. Google ScholarDigital Library
- {Eldred 59} Eldred, R. D., "Test Routines based on Symbolic Logic Statements," Journal ACM, Vol. 6, No. 1, pp. 33--37, Jan. 1959. Google ScholarDigital Library
- {Hamzaoglu 99} Hamzaoglu, I., and J. H. Patel, "Reducing Test Application Time for Full Scan Embedded Cores," Proc. Intl. Symp. Fault-Tolerant Computing, pp. 260--267, 1999. Google ScholarDigital Library
- {Heath 04} Heath, M. W., W. P. Burleson and I. G. Harris, "Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC's," Proc. Design, Automation and Test in Europe, pp. 1532--1546, 2004. Google ScholarDigital Library
- {Iyer 05} Iyer, R. K., N. Nakka, Z. Kalbarczyk and S. Mitra, "Recent Advances and New Avenues in Hardware-Level Reliability Support," IEEE MICRO, Vol. 25, No. 6, pp. 18--29, Nov.-Dec. 2005. Google ScholarDigital Library
- {Josephson 01} Josephson, D., S. Poehlman and V. Govan, "Debug Methodology for the McKinley Processor," Proc. Intl. Test Conf., pp. 451--460, 2001. Google ScholarDigital Library
- {Josephson 06} Josephson, D., "The Good, the Bad, and the Ugly of Silicon Debug," Proc. Design Automation Conf., pp. 3--6, 2006. Google ScholarDigital Library
- {Keshava 10} Keshava, K., N. Hakim and C. Prudvi, "Post-Silicon Validation Challenges: How EDA and Academia Can Help," Proc. Design Automation Conf., 2010. Google ScholarDigital Library
- {Ko 08a} Ko, H. F., and N. Nicolici, "Automated Trace Signals Identification and State Restoration for Improving Observability in Post-silicon Validation," Proc. Design Automation and Test in Europe, pp. 1298--1303, 2008. Google ScholarDigital Library
- {Ko 08b} Ko, H. F., A. B. Kinsman and N. Nicolici, "Distributed Embedded Logic Analysis for Post-silicon Validation of SOCs," Proc. Intl. Test Conf., 2008.Google Scholar
- {Koenemann 91} Koenemann, B., "LFSR-Coded Test Patterns for Scan Designs," Proc. European Test Conf., pp. 237--242, 1991.Google Scholar
- {Krstic 02} Krstic, A., W. C. Lai, K. T. Cheng, L. Chen and S. Dey, "Embedded Software-Based Self-Test for Programmable Core-Based Designs," IEEE Design and Test of Computers, Vol. 19, No. 4, pp. 18--27, July-Aug. 2002. Google ScholarDigital Library
- {Li 09} Li, Y., Y. M. Kim, E. Mintarno, D. S. Gardner and S. Mitra, "Overcoming Early-Life Failure and Aging Challenges for Robust System Design," IEEE Design and Test of Computers, Vol. 26, No. 6, pp. 28--39, Nov.-Dec. 2009. Google ScholarDigital Library
- {Li 10} Li, W., A. Forin and S. A. Seshia, "Scalable Specification Mining for Verification and Diagnosis," Proc. Design Automation Conf., 2010. Google ScholarDigital Library
- {Liu 09} Liu, X., and Q. Xu, "Trace Signal Selection for Visibility Enhancement in Post-Silicon Validation," Proc. Design Automation and Test in Europe, pp. 1338--1343, 2009. Google ScholarDigital Library
- {Ma 95} Ma, S. C., P. Franco and E. J. McCluskey, "An Experimental Test Chip to Evaluate Test Techniques: Experimental Results," Proc. Intl. Test Conf., pp. 663--672, 1995. Google ScholarDigital Library
- {Malik 09} Malik, S., and L. Zhang, "Boolean Satisfiability: From Theoretical Hardness to Practical Success," Communications of the ACM, Vol. 52, No. 8, pp. 76--82, Aug. 2009. Google ScholarDigital Library
- {Mitra 02} Mitra, S., and K. S. Kim, "X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction," Proc. Intl. Test Conf., pp. 311--320, 2002. Google ScholarDigital Library
- {Mitra 04} Mitra, S., and K. S. Kim, "X-Compact: An Efficient Response Compaction Technique," IEEE Trans. CAD, Vol. 23, issue 3, pp. 421--432, March 2004. Google ScholarDigital Library
- {Mitra 10} Mitra, S., "Robust System Design," Proc. Intl. Conf. VLSI Design, pp. 434--439, 2010. Google ScholarDigital Library
- {Moore 98} Moore, J., T. Lynch, and M. Kaufmann, "A mechanically checked proof of the AMD5 K86(TM) floating-point division program," IEEE Trans. Computers, Vol. 47, No. 9, pp. 913--926, Sept. 1998. Google ScholarDigital Library
- {Naffziger 06} Naffziger, S., B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E. Alon and M. Horowitz, "The Implementation of a 2-core, Multi-threaded Itanium Family Processor," IEEE Journal Solid-State Circuits, Vol. 41, No. 1, pp. 197--209, Jan. 2006.Google ScholarCross Ref
- {Park 08} Park, S. B., and S. Mitra "IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization in Processors," Proc. Design Automation Conf., 2008. Google ScholarDigital Library
- {Park 09} Park, S. B., T. Hong and S. Mitra, "Post-Silicon Bug Localization in Processors using Instruction Footprint Recording and Analysis (IFRA)," IEEE Trans. CAD, Vol. 28, Issue 10, pp. 1545--1558, Oct. 2009. Google ScholarDigital Library
- {Park 10a} Park, S. B., and S. Mitra, "Post-silicon Bug Localization for Processors using IFRA," Communications of the ACM, Vol. 53, No. 2, pp. 106--113, Feb. 2010. Google ScholarDigital Library
- {Park 10b} Park, S. B., A. Bracy, H. Wang and S. Mitra, "BLoG: Post-Silicon Bug Localization in Processors using Bug Localization Graphs," Proc. Design Automation Conf, 2010. Google ScholarDigital Library
- {Parvathala 02} Parvathala, P., K. Maneparambil and W. Lindsay, "FRITS --- A Microprocessor Functional BIST Method," Proc. Intl. Test Conf., pp. 590--598, 2002. Google ScholarDigital Library
- {Patra 07} Patra, P., "On the Cusp of a Validation Wall," IEEE Design and. Test of Computers, Vol. 24, No. 2, pp. 193--196, March-April 2007. Google ScholarDigital Library
- {Pnueli 77} Pnueli, A., "The Temporal Logic of Programs," Proc. Symp. Foundations of Computer Science, pp. 46--57, 1977. Google ScholarDigital Library
- {Sarangi 06} Sarangi, S., B. Greskamp and J. Torrellas, "CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging," Proc. Dependable Systems and Networks, pp. 301--312, 2006. Google ScholarDigital Library
- {Seshia 07} Seshia, S. A., W. Li and S. Mitra, "Verification-Guided Soft Error Resilience," Proc. Design Automation and Test in Europe, pp. 1442--1447, 2007. Google ScholarDigital Library
- {Shen 98} Shen, J., and J. A. Abraham, "Native Mode Functional Test Generation for Processors with Applications to Self Test and Design Validation," Proc. Intl. Test Conf., pp. 990--999, 1998. Google ScholarDigital Library
- {Silas 03} Silas, I., I. Frumkin, E. Hazan, E. Mor and G. Zobin, "System-Level Validation of the Intel Pentium M Processor," Intel Technology Journal, Vol. 7, No. 2., pp. 37--43, May 2003.Google Scholar
- {Siewiorek 98} Siewiorek, D. P., and R. S. Swarz, Reliable Computer Systems: Design and Evaluation, A. K. Peters, 1998. Google ScholarDigital Library
- {Vardi 08} Vardi, M., "From Church and Prior to PSL," Proc. 25 Years of Model Checking, pp. 150--171, 2008. Google ScholarDigital Library
- {Wagner 08} Wagner, I., V. Bertacco and T. Austin, "Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors," IEEE Trans. CAD, Vol. 27, Issue 2, pp. 380--393, Feb 2008. Google ScholarDigital Library
- {Williams 73} Williams, M. J. Y., and J. B. Angell, "Enhancing Testability of Large Scale Integrated Circuits via Test Points and Additional Logic," IEEE Trans. Computers, Vol. C-22, Issue 1, pp. 46--60, Jan. 1973. Google ScholarDigital Library
- {Yerramilli 06} Yerramilli, S., "Addressing Post-Silicon Validation Challenge: Leverage Validation and Test Synergy," Keynote, Intl. Test Conf., 2006.Google Scholar
Index Terms
- Post-silicon validation opportunities, challenges and recent advances
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