ABSTRACT
NBTI has been a major aging mechanism for advanced CMOS technology and PBTI is also looming as a big concern. This work first proposes a compact on-chip sensor design that tracks both NBTI and PBTI for both logic and SRAM circuits. Embedded in an SRAM array the sensor takes the form of a 6T SRAM cell and is at least 30x smaller than previous designs. Extensively reusing the SRAM peripheral circuitry minimizes control logic overhead. Sensing overhead is further amortized as the sensors can be both reconfigured and recycled as functional SRAM cells, potentially increasing SRAM yield when other bit cells fail due to initial process variation or long time aging effects. The paper also proposes a variation-aware sensor system design methodology by quantifying and leveraging the tradeoff between the size and number of sensors and the system sensing precision. Design examples show that a system of 500 sensors can achieve 4mV precision with 98.8% confidence, and a system of 1K sensors designed for 1M SRAM bit cells achieves 2000x area overhead reduction compared to a worst-case based approach.
- A. Davoodi et al., "Variability driven gate sizing for binning yield optimization," DAC, 2006. Google ScholarDigital Library
- X. Yang et al., "Combating nbti degradation via gate sizing," ISQED, 2007. Google ScholarDigital Library
- A. Cabe, et al., "Small embeddable nbti sensors (sens) for tracking on-chip performance decay," ISQED, 2009. Google ScholarDigital Library
- M. Agarwal, et al., "Circuit failure prediction and its application to transistor aging," VLSI Test Symposium, 2007. Google ScholarDigital Library
- J. Keane, et al., "An on-chip nbti sensor for measuring PMOS threshold voltage degradation," ISLPED, 2007. Google ScholarDigital Library
- Z. Qi, et al., "NBTI resilient circuits using adaptive body biasing," GLSVLSI, 2008. Google ScholarDigital Library
- E. Karl, et al., "Compact in-situ sensors for monitoring negative bias temperature instability effect and oxide degradation," ISSCC, 2008.Google Scholar
- E. Karl, et al., "Reliability modeling and management in dynamic microprocessor-based systems," DAC, 2006. Google ScholarDigital Library
- E. Karl, et al., "Analysis of system-level reliability factors and implications on real-time monitoring methods for oxide breakdown device failures," ISQED, 2008. Google ScholarDigital Library
- R. Vattikonda, et al., "Modeling and minimization of PMOS NBTI effect for robust nanometer design," DAC, 2006. Google ScholarDigital Library
- S. Kumar et al., "Impact of NBTI on SRAM read stability and design for reliability," ISQED, 2006. Google ScholarDigital Library
- S. Rauch, "The statistics of nbti-induced V T and β-mismatch shifts in pMOSFETs," IEEE Trans. on Device and Materials Reliability, 2002.Google Scholar
- A. Krishnan, et al., "SRAM cell static noise margin and vmin sensitivity to transistor degradation," IEDM, 2006.Google Scholar
- SRAM-based NBTI/PBTI sensor system design
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