ABSTRACT
Since 2005, processor designers have increased core counts to exploit Moore's Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to which the shift to multicore parts is partially a response, may soon limit multicore scaling just as single-core scaling has been curtailed. This paper models multicore scaling limits by combining device scaling, single-core scaling, and multicore scaling to measure the speedup potential for a set of parallel workloads for the next five technology generations. For device scaling, we use both the ITRS projections and a set of more conservative device scaling parameters. To model single-core scaling, we combine measurements from over 150 processors to derive Pareto-optimal frontiers for area/performance and power/performance. Finally, to model multicore scaling, we build a detailed performance model of upper-bound performance and lower-bound core power. The multicore designs we study include single-threaded CPU-like and massively threaded GPU-like multicore chip organizations with symmetric, asymmetric, dynamic, and composed topologies. The study shows that regardless of chip organization and topology, multicore scaling is power limited to a degree not widely appreciated by the computing community. Even at 22 nm (just one year from now), 21% of a fixed-size chip must be powered off, and at 8 nm, this number grows to more than 50%. Through 2024, only 7.9x average speedup is possible across commonly used parallel workloads, leaving a nearly 24-fold gap from a target of doubled performance per generation.
Supplemental Material
- G. M. Amdahl. Validity of the single processor approach to achieving large-scale computing capabilities. In AFIPS '67. Google ScholarDigital Library
- O. Azizi, A. Mahesri, B. C. Lee, S. J. Patel, and M. Horowitz. Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. In ISCA '10. Google ScholarDigital Library
- A. Bakhoda, G. L. Yuan, W. W. L. Fung, H. Wong, and T. M. Aamodt. Analyzing CUDA workloads using a detailed GPU simulator. In ISPASS '09.Google Scholar
- M. Bhadauria, V. Weaver, and S. McKee. Understanding PARSEC performance on contemporary CMPs. In IISWC '09. Google ScholarDigital Library
- C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: Characterization and architectural implications. In PACT '08. Google ScholarDigital Library
- S. Borkar. Thousand core chips: a technology perspective. In DAC '07. Google ScholarDigital Library
- S. Borkar. The exascale challenge. Keynote at International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2010.Google Scholar
- K. Chakraborty. Over-provisioned Multicore Systems. PhD thesis, University of Wisconsin-Madison, 2008. Google ScholarDigital Library
- S. Cho and R. Melhem. Corollaries to Amdahl's law for energy. Computer Architecture Letters, 7 (1), January 2008. Google ScholarDigital Library
- E. S. Chung, P. A. Milder, J. C. Hoe, and K. Mai. Single-chip heterogeneous computing: Does the future include custom logic, FPGAs, and GPUs? In phMICRO '10. Google ScholarDigital Library
- R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. LeBlanc. Design of ion-implanted mosfet's with very small physical dimensions. IEEE Journal of Solid-State Circuits, 9, October 1974.Google ScholarCross Ref
- H. Esmaeilzadeh, T. Cao, Y. Xi, S. M. Blackburn, and K. S. McKinley. Looking back on the language and hardware revolutions: measured power, performance, and scaling. In ASPLOS '11. Google ScholarDigital Library
- Z. Guz, E. Bolotin, I. Keidar, A. Kolodny, A. Mendelson, and U. C. Weiser. Many-core vs. many-thread machines: Stay away from the valley. IEEE Computer Architecture Letters, 8, January 2009. Google ScholarDigital Library
- M. Hempstead, G.-Y. Wei, and D. Brooks. Navigo: An early-stage model to study power-contrained architectures and specialization. In MoBS '09.Google Scholar
- M. D. Hill and M. R. Marty. Amdahl's law in the multicore era. Computer, 41 (7), July 2008. Google ScholarDigital Library
- M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein. Scaling, power, and the future of CMOS. In IEDM '05.Google Scholar
- E. Ipek, M. Kirman, N. Kirman, and J. F. Martinez. Core fusion: accommodating software diversity in chip multiprocessors. In ISCA '07. Google ScholarDigital Library
- ITRS. International technology roadmap for semiconductors, 2010 update, 2011. URL http://www.itrs.net.Google Scholar
- C. Kim, S. Sethumadhavan, M. S. Govindan, N. Ranganathan, D. Gulati, D. Burger, and S. W. Keckler. Composable lightweight processors. In MICRO '07. Google ScholarDigital Library
- Lee, Jung, and Shin}LeeJ.-G. Lee, E. Jung, and W. Shin. An asymptotic performance/energy analysis and optimization of multi-core architectures. In ICDCN '09,. Google ScholarDigital Library
- Lee:ISCA10V. W. Lee et al. Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU. In ISCA '10,. Google ScholarDigital Library
- G. Loh. The cost of uncore in throughput-oriented many-core processors. In ALTA '08.Google Scholar
- G. E. Moore. Cramming more components onto integrated circuits. phElectronics, 38 (8), April 1965.Google Scholar
- K. Nose and T. Sakurai. Optimization of VDD and VTH for low-power and high speed applications. In phASP-DAC '00. Google ScholarDigital Library
- SPEC. Standard performance evaluation corporation, 2011. URL http://www.spec.org.Google Scholar
- A. M. Suleman, O. Mutlu, M. K. Qureshi, and Y. N. Patt. Accelerating critical section execution with asymmetric multi-core architectures. In ASPLOS '09. Google ScholarDigital Library
- G. Venkatesh, J. Sampson, N. Goulding, S. Garcia, V. Bryksin, J. Lugo-Martinez, S. Swanson, and M. B. Taylor. Conservation cores: reducing the energy of mature computations. In ASPLOS '10. Google ScholarDigital Library
- D. H. Woo and H.-H. S. Lee. Extending Amdahl's law for energy-efficient computing in the many-core era. Computer, 41 (12), December 2008. Google ScholarDigital Library
Index Terms
- Dark silicon and the end of multicore scaling
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