skip to main content
10.1145/2024724.2024929acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

A fault-tolerant NoC scheme using bidirectional channel

Published:05 June 2011Publication History

ABSTRACT

A novel Bidirectional Fault-Tolerant NoC (BFT-NoC) architecture capable of mitigating both static and dynamic channel failures is proposed. In a traditional NoC platform, a faulty data channel will force blocked packets to make costly detours, resulting in significant performance hits. In this work, novel fault-tolerance measures for a bidirectional NoC platform are proposed. The dynamically reconfigurable bidirectional channels of the BFT-NoC offer great flexibility to contain data-link permanent or transient faults while incurring negligible performance loss. Potential performance advantages in terms of failure rate reduction and reliability enhancement of the BFT-NoC architecture are carefully analyzed. Extensive experimental results clearly validate the fault-tolerance performance of BFT-NoC at both synthetic and real world network traffic patterns.

References

  1. L. Benini and G. De Micheli, "Networks on Chips: a New SoC paradigm," IEEE Computer, Vol. 35(1), pp. 70--78, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. T. Schonwald, J. Zimmermann, O. Bringmann, and W. Rosenstiel, "Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures," in Proc. of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, pp. 527--534, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. A. Kohler, G. Schley, and M. Radetzki, "Fault Tolerant Network on Chip Switching With Graceful Performance Degradation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, pp. 883--896, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Z. Zhen, A. Greiner, and S. Taktak, "A Reconfigurable Routing Algorithm for a Fault-Tolerant 2D-Mesh Network-on-Chip," in Proc. of the 45th Design Automation Conference, pp. 441--446, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester, and D. Blaauw, "A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs," in Proc. of the 12nd Design, Automation and Test in Europe Conference and Exhibition, pp. 21--26, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Y. C. Lan, S. H. Lo, Y. C. Lin, Y. H. Hu, and S. J. Chen, "BiNoC: A Bidirectional NoC Architecture with Dynamic Self-Reconfigurable Channel," in Proc. of the 3rd ACM/IEEE International Symposium on Networks-on-Chip, pp. 266--275, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. M. H. Cho, M. Lis, M. Kinsy, K. S. Shim, T. Wen, and S. Devadas, "Oblivious Routing in On-Chip Bandwidth-Adaptive Networks," in Proc. of the 18th International Conference on Parallel Architectures and Compilation Techniques, pp. 181--190, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. L. Benini and G. De Micheli, Networks on Chips: Technology and Tools, Morgan Kauffmann, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. M. Cuviello, S. Dey, X. Bai, and Y. Zhao, "Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects," in Proc. of the IEEE/ACM International Conference on Computer-Aided Design, pp. 297--303, 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. G. M. Chiu, "The Odd-Even Turn Model for Adaptive Routing," IEEE Trans. Parallel and Distributed Systems, Vol. 11, pp. 729--738, 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. G. Michelogiannakis, D. Sanchez, W. J. Dally, and C. Kozyrakis, "Evaluating Bufferless Flow Control for On-Chip Networks," in Proc. of the 4th ACM/IEEE International Symposium on Networks-on-Chip, pp. 9--16, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. R. Dick, "Embedded System Synthesis Benchmark Suites (E3S)," http://ziyang.eecs.umich.edu/~dickrp/e3s/.Google ScholarGoogle Scholar

Index Terms

  1. A fault-tolerant NoC scheme using bidirectional channel

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in
    • Published in

      cover image ACM Conferences
      DAC '11: Proceedings of the 48th Design Automation Conference
      June 2011
      1055 pages
      ISBN:9781450306362
      DOI:10.1145/2024724

      Copyright © 2011 ACM

      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 5 June 2011

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • research-article

      Acceptance Rates

      Overall Acceptance Rate1,770of5,499submissions,32%

      Upcoming Conference

      DAC '24
      61st ACM/IEEE Design Automation Conference
      June 23 - 27, 2024
      San Francisco , CA , USA

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader