Lois Orosa
Skip Abstract Section
Abstract
With the advent of chip multiprocessors, new techniques have been developed to make parallel programing easier and more reliable. New parallel programing paradigms and new methods of making the execution of programs more efficient and more reliable have been developed. Usually, these improvements require hardware support to avoid a system slowdown.
Signatures based on Bloom filters are widely used as hardware support for parallel programing in chip multiprocessors. Signatures are used in Transactional Memory, thread-level speculation, parallel debugging, deterministic replay and other tools and applications. The main limitation of hardware signatures is the lack of flexibility: if signatures are designed with a given configuration, tailored to the requirements of a specific tool or application, it is likely that they do not fit well for other different requirements.
In this paper a new hardware signature organization, called Flexible Signatures (FlexSig), is proposed. FlexSig can change dynamically the resources assigned to a given signature and the number of signatures in the system, by redistributing the available hardware resources according to the system requirements. This allows higher flexibility than with traditional fixed-resources signatures based on Bloom filters, while maintaining a low false positive rate.
FlexSig has been evaluated by comparing it with signatures based on parallel Bloom filters, and we conclude that FlexSig outperforms (in terms of false positive rate) conventional parallel Bloom filters in most cases, due to its ability to use all the signature resources available.
- Adve, S. V., Hill, M. D., Miller, B. P., and Netzer, R. H. B. 1991. Detecting data races on weak memory systems. In Proceedings of the 18th Annual International Symposium on Computer Architecture. (ISCA '91). ACM, New York, NY, 234--243. Google Scholar
Digital Library
- Almeida, P., Baquero, C., Preguica, N., and Hutchison, D. 2007. Scalable bloom filters. Infor. Process. Lett. 101, 6, 255--261. Google ScholarDigital Library
- Ananian, C. S., Asanovic, K., Kuszmaul, B. C., Leiserson, C. E., and Lie, S. 2005. Unbounded transactional memory. In HPCA '05: Proceedings of the 11th International Symposium on High-Performance Computer Architecture. IEEE Computer Society, Los Alamitos, CA, 316--327. Google ScholarDigital Library
- Bienia, C., Kumar, S., Singh, J. P., and Li, K. 2008. The parsec benchmark suite: characterization and architectural implications. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, (PACT '08). ACM, New York, NY, 72--81. Google ScholarDigital Library
- Bloom, B. H. 1970. Space/time trade-offs in hash coding with allowable errors. Comm. ACM 13, 422--426. Google ScholarDigital Library
- Cao Minh, C., Chung, J., Kozyrakis, C., and Olukotun, K. 2008. STAMP: Stanford transactional applications for multi-processing. In IISWC '08: Proceedings of the IEEE International Symposium on Workload Characterization.Google Scholar
- Carter, J. L. and Wegman, M. N. 1977. Universal classes of hash functions (extended abstract). In Proceedings of the 9th Annual ACM Symposium on Theory of Computing, (STOC '77). ACM, New York, NY, 106--112. Google ScholarDigital Library
- Casper, J., Oguntebi, T., Hong, S., Bronson, N. G., Kozyrakis, C., and Olukotun, K. 2011. Hardware acceleration of transactional memory on commodity systems. In Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems, (ASPLOS '11). ACM, New York, NY, 27--38. Google ScholarDigital Library
- Ceze, L., Tuck, J., Montesinos, P., and Torrellas, J. 2007. Bulksc: bulk enforcement of sequential consistency. In Proceedings of ISCA. Google ScholarDigital Library
- Ceze, L., Tuck, J., Torrellas, J., and Cascaval, C. 2006. Bulk disambiguation of speculative threads in multiprocessors. In Proceedings of the 33rd Annual International Symposium on Computer Architecture. IEEE Computer Society, 238. Google ScholarDigital Library
- Chang, F., chang Feng, W., and Li, K. 2004. Approximate caches for packet classification. In INFOCOM 2004. Proceedings of the 23th Annual Joint Conference of the IEEE Computer and Communications Societies. Vol. 4, 2196--2207.Google Scholar
- Chang, F., Li, K., and chang Feng, W. 2004. Approximate caches for packet classification. In Proceedings of INFOCOM.Google ScholarCross Ref
- Choi, J.-D., Lee, K., Loginov, A., O'Callahan, R., Sarkar, V., and Sridharan, M. 2002. Efficient and precise datarace detection for multithreaded object-oriented programs. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, (PLDI '02). ACM, New York, NY, 258--269. Google ScholarDigital Library
- Choi, W. and Draper, J. 2011. Implementation of unified signatures for transactional memory systems. In Proceedings of the IEEE International Parallel and Distributed Processing Symposium.Google Scholar
- Fan, L., Cao, P., Almeida, J., and Broder, A. Z. 2000. Summary cache: A scalable wide-area web cache sharing protocol. IEEE/ACM Trans. Netw. 8, 281--293. Google ScholarDigital Library
- Hammond, L., Wong, V., Chen, M., Carlstrom, B. D., Davis, J. D., Hertzberg, B., Prabhu, M. K., Wijaya, H., Kozyrakis, C., and Olukotun, K. 2004. Transactional memory coherence and consistency. In Proceedings of the 31st Annual International Symposium on Computer Architecture, (ISCA '04). IEEE Computer Society, Los Alamitos, CA, 102. Google ScholarDigital Library
- Herlihy, M. and Moss, J. 1993. Transactional memory: Architectural support for lock-free data structures. In Proceedings of the 20th Annual International Symposium on Computer Architecture. ACM, 300. Google ScholarDigital Library
- keung Luk, C., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Janapa, V., and Hazelwood, R. K. 2005. Pin: Building customized program analysis tools with dynamic instrumentation. In Programming Language Design and Implementation. ACM, 190--200. Google ScholarDigital Library
- Lev, Y. and Moir, M. 2006. Debugging with transactional memory. In Proceedings of the 1st ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing.Google Scholar
- Lucia, B., Devietti, J., Strauss, K., and Ceze, L. 2008. Atom-aid: Detecting and surviving atomicity violations. In Proceedings of the 35th Annual International Symposium on Computer Architecture, (ISCA '08). IEEE Computer Society, Los Alamitos, CA, 277--288. Google ScholarDigital Library
- Mehrara, M., Hao, J., Hsu, P.-C., and Mahlke, S. 2009. Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, (PLDI '09). ACM, New York, NY, 166--176. Google ScholarDigital Library
- Muzahid, A., Suárez, D., Qi, S., and Torrellas, J. 2009. Sigrace: signature-based data race detection. In ISCA '09: Proceedings of the 36th Annual International Symposium on Computer Architecture. ACM, New York, NY, 337--348. Google ScholarDigital Library
- Netzer, R. H. B. and Miller, B. P. 1991. Improving the accuracy of data race detection. In Proceedings of the 3th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, (PPOPP '91). ACM, New York, NY, 133--144. Google ScholarDigital Library
- Netzer, R. N. and Miller, B. P. 1989. Detecting data races in parallel program executions. In Proceedings of the 1990 Workshop on Advances in Languages and Compilers for Parallel Computing. MIT Press, 109--129.Google Scholar
- O'Callahan, R. and Choi, J.-D. 2003. Hybrid dynamic data race detection. In Proceedings of the 9th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, (PPoPP '03). ACM, New York, NY, 167--178. Google ScholarDigital Library
- Prvulovic, M. and Torrellas, J. 2003. Reenact: using thread-level speculation mechanisms to debug data races in multithreaded codes. In Proceedings of the 30th Annual International Symposium on Computer Architecture, (ISCA '03). ACM, New York, NY, 110--121. Google ScholarDigital Library
- Quislant, R., Gutierrez, E., Plata, O., and Zapata, E. L. 2009. Improving signatures by locality exploitation for transactional memory. In Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques. IEEE Computer Society, Los Alamitos, CA, 303--312. Google ScholarDigital Library
- Ramakrishna, M. V., Fu, E., and Bahcekapili, E. 1997. Efficient hardware hashing functions for high performance computers. IEEE Trans. Comput. 46, 1378--1381. Google ScholarDigital Library
- Ratanaworabhan, P., Burtscher, M., Kirovski, D., Zorn, B., Nagpal, R., and Pattabiraman, K. 2009. Detecting and tolerating asymmetric races. In PPoPP '09: Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. ACM, New York, NY, 173--184. Google ScholarDigital Library
- Reynolds, P. and Vahdat, A. 2003. Efficient peer-to-peer keyword searching. In Proceedings of the ACM/IFIP/USENIX International Conference on Middleware, (Middleware '03). Springer-Verlag, Berlin, 21--40. Google ScholarDigital Library
- Rhea, S. and Kubiatowicz, J. 2002. Probabilistic location and routing. In INFOCOM 2002. Proceedings of the 21st Annual Joint Conference of the IEEE Computer and Communications Societies. IEEE. Vol. 3, 1248--1257.Google Scholar
- Riegel, T., Fetzer, C., and Felber, P. 2007. Time-based transactional memory with scalable time bases. In Proceedings of the 19th Annual ACM Symposium on Parallel Algorithms and Architectures, (SPAA '07). ACM, New York, NY, 221--228. Google ScholarDigital Library
- Sanchez, D., Yen, L., Hill, M. D., and Sankaralingam, K. 2007. Implementing signatures for transactional memory. In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, (MICRO 40). IEEE Computer Society, Los Alamitos, CA, 123--133. Google ScholarDigital Library
- Sanyal, S., Roy, S., Cristal, A., Unsal, O. S., and Valero, M. 2009. Dynamically filtering thread-local variables in lazy-lazy hardware transactional memory. In Proceedings of the 11th IEEE International Conference on High Performance Computing and Communications. IEEE Computer Society, Los Alamitos, CA, 171--179. Google ScholarDigital Library
- Shenghua, Z., Zheng, Q., Yuan, Z., and Xiaolan, P. 2009. A cascade hash design of bloom filter for signature detection. In Proceedings of the International Forum on Information Technology and Applications, (IFITA '09). Vol. 2, 559--562.Google Scholar
- Spear, M. F., Michael, M. M., and von Praun, C. 2008. Ringstm: scalable transactions with a single atomic instruction. In Proceedings of the 20th Annual Symposium on Parallelism in Algorithms and Architectures, (SPAA '08). ACM, New York, NY, 275--284. Google ScholarDigital Library
- Tuck, J., Ahn, W., Ceze, L., and Torrellas, J. 2008. Softsig: software-exposed hardware signatures for code analysis and optimization. In Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, (ASPLOS XIII). ACM, New York, NY, 145--156. Google ScholarDigital Library
- Yen, L. 2009. Signatures in transactional memory systems. Ph.D. thesis, Madison, WI. Google ScholarDigital Library
- Yen, L., Bobba, J., Marty, M. R., Moore, K. E., Volos, H., Hill, M. D., Swift, M. M., and Wood, D. A. 2007. Logtm-se: Decoupling hardware transactional memory from caches. In Proceedings of the IEEE 13th International Symposium on High Performance Computer Architecture. IEEE Computer Society, Los Alamitos, CA, 261--272. Google ScholarDigital Library
- Yen, L., Draper, S. C., and Hill, M. D. 2008. Notary: Hardware techniques to enhance signatures. In Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture, (MICRO 41). IEEE Computer Society, Los Alamitos, CA, 234--245. Google ScholarDigital Library
- Yu, Y., Rodeheffer, T., and Chen, W. 2005. Racetrack: efficient detection of data race conditions via adaptive tracking. In Proceedings of the 20th ACM Symposium on Operating Systems Principles, (SOSP '05). ACM, New York, NY, 221--234. Google ScholarDigital Library
- Zhou, P., Teodorescu, R., and Zhou, Y. 2007. Hard: Hardware-assisted lockset-based race detection. In Proceedings of the IEEE 13th International Symposium on High Performance Computer Architecture. IEEE Computer Society, Los Alamitos, CA, 121--132. Google ScholarDigital Library
Index Terms
- FlexSig: Implementing flexible hardware signatures
Recommendations
Shorter Quasi-Adaptive NIZK Proofs for Linear Subspaces
We define a novel notion of quasi-adaptive non-interactive zero-knowledge (NIZK) proofs for probability distributions on parameterized languages. It is quasi-adaptive in the sense that the common reference string (CRS) generator can generate the CRS ...
On-line non-transferable signatures revisited
PKC'11: Proceedings of the 14th international conference on Practice and theory in public key cryptography conference on Public key cryptographyUndeniable signatures, introduced by Chaum and van Antwerpen, and designated confirmer signatures, introduced by Chaum, allow a signer to control the verifiability of his signatures by requiring a verifier to interact with the signer to verify a ...
Signature Scheme in Multi-User Setting
Recently, Boneh and Boyen proposed a new provably secure short signature scheme under the q-strong Diffie-Hellman assumption without random oracles. This scheme is based on bilinear map which is different from Cramer-Shoup signature scheme (which is ...
Comments