- 1.E. J. Aas, K. Klingsheim, and T. Steen. Quantifying design quality. In Proceedings of EURO ASIC, pages 172-177, 1992.Google ScholarCross Ref
- 2.C. L. Berman and L. H. Trevillyan. Functional comparison of logic designs for vlsi circuits. In Intl. Test Conference, pages 456-459, 1989.Google ScholarCross Ref
- 3.K. Brace. Efficient implementation of a bdd package. In Design Automation Conference, pages 40-45, 1990. Google ScholarDigital Library
- 4.D. Brand. Verification of large synthesized designs. In Intl. Conference on Computer-aided Design, pages 534-537, 1993. Google ScholarDigital Library
- 5.F. Brglez and H. Fujiwara. A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran. In Special Session on the 1985 IEEE Intl. Symposium on Circuits ~ Systems, 1985.Google Scholar
- 6.R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, pages 677-691, Aug. 1986. Google ScholarDigital Library
- 7.J. Jain et al. Indexed bdds: Algorithmic advances in techniques to represent to represent and verify boolean functions. Technical Report UT-CERC-TR- JAA-93-02, Comp. Eng. Research Center, 1993.Google Scholar
- 8.R. Drechsler et al. Efficient representation and manipulation of switching functions based on ordered kronecker functional decision diagrams. In Design Automation Conference, pages 415-419, 1994. Google ScholarDigital Library
- 9.T.R. Shiple et al. Heuristic minimization of bdds using don't cares. In Design Automation Conference, pages 225-231, 1994. Google ScholarDigital Library
- 10.H. Fujiwara and T. Shimono. On the acceleration of test generation algorithms. In Intl. Symposium on Fault-tolerant Computing, pages 98-105, 1983.Google ScholarDigital Library
- 11.W. Kunz. Hannibal: An efficient tool for logic verification, based on recursive learning. In Intl. Conference on Computer-aided Design, pages 538-543, 1993. Google ScholarDigital Library
- 12.W. Kunz and P. Menon. Multi-level logic optimization by implication analysis. In Intl. Conference on Computer-aided Design, pages 6-13, November, 1994. Google ScholarDigital Library
- 13.W. Kunz and D. K. Pradhan. Recursive learning: A new implication technique for efficient solutions to CAD problems - test, verification, and optimization. In IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, Vol. 13, No. 9, pages 1143-1157, September, 1994.Google ScholarDigital Library
- 14.S. Malik, A. Wang, R. Brayton, and A. Sangiovanni- Vincentelli. Logic verification using binary decision diagrams in a logic synthesis environment. In Intl. Conference on Computer-aided Design, pages 6-9, Nov. 1988.Google ScholarCross Ref
- 15.M. R. Mercer, R. Kapur, D. E. Ross. Functional approaches to generate orderings for efficient symbolic representations. In Design Automation Conference, 1992. Google ScholarDigital Library
- 16.R. Rudell. Dynamic variable ordering for ordered binary decision diagrams. In Intl. Conference on Computer-aided Design, pages 42-47, Nov. 1993. Google ScholarDigital Library
- 17.A. Shen, S. Devadas, and A. Ghosh. Probabilistic construction and manupulation of free boolean diagrams. In Intl. Conference on Computer-aided Design, 1993. Google ScholarDigital Library
- 18.D. Stoffel, W. Kunz, S. Gerber. Multi-level Logic Synthesis by And-Or-Graphs. Technical Report, MPI-I-95-602, Max-Planck Fault-Tolerant Computing Group, 1995.Google Scholar
- 19.G. J. Tromp and A. J. van de Goor. Logic synthesis of 100-percent testable logic networks. In Intl. Conerence on Computer-aided Design, 1991. Google ScholarDigital Library
- 20.R. Wei and A. L. Sangiovanni-Vincentelli. Proteus: A logic verification system for combinational circuits. In Intl. Test Conference, 1986.Google Scholar
Index Terms
- Novel verification framework combining structural and OBDD methods in a synthesis environment
Recommendations
Environment Synthesis for Compositional Model Checking
ICCD '02: Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)Modeling the environment of a design module under verification is a known practical problem in compositional verification. In this paper, we propose an approach to translate an ACTL specification into such an environment. Throughout the translation, we ...
Effectively Combining Software Verification Strategies: Understanding Different Assumptions
ISSRE '06: Proceedings of the 17th International Symposium on Software Reliability EngineeringIn this paper we describe an experiment in which inconsistent results between two tools for testing formal models (and a third used to determine which of the two was correct) led us to a more careful look at the way each tool was being used and a ...
Comments