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Standard cell sizing for subthreshold operation

Published:03 June 2012Publication History

ABSTRACT

Process variability severely impacts the performance of circuits operating in the subthreshold domain. Among other reasons, this mainly stems from the fact that subthreshold current follows a widely spread Log-Normal distribution. In this paper we introduce a new transistor sizing methodology for standard cells. Our premise relies on balancing the N and P network currents based on statistical formulations. Our approach renders more robust cells. We observe up to 57% better performance and 69% lower energy consumption on a set of ISCAS circuits when they are synthesized with our library as opposed to a commercial library in a CMOS 90nm technology.

References

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        cover image ACM Conferences
        DAC '12: Proceedings of the 49th Annual Design Automation Conference
        June 2012
        1357 pages
        ISBN:9781450311991
        DOI:10.1145/2228360

        Copyright © 2012 ACM

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        Publication History

        • Published: 3 June 2012

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