- 1.M. Alidina, et al., "Precomputation-based sequential logic optimization for low power," in ICCAD, Proceedings of the International Conference on Computer-Aided Design, pp. 74-80, Nov. 1994. Google ScholarDigital Library
- 2.L. Benini, P. Siegel and G. De Micheli, "Automatic synthesis of gated clocks for power reduction in sequential circuits" IEEE Design and Test of Computers, pp. 32-40, Dic. 1994.Google ScholarCross Ref
- 3.A. Shen, A. Ghosh, S. Devadas, and K. Keutzer, "On average power dissipation and random pattern testability of CMOS combinationallogic networks," in ICCAD, Proceedings of the International Conference on Computer-Aided Design, pp. 402-407, Nov. 1992. Google ScholarDigital Library
- 4.C. Tsui, M. Pedram, and A. Despain, "Technology decomposition and mapping targeting low power dissipation," in DAC, Proceedings of the Design Automation Conference, pp. 68-73, June 1993. Google ScholarDigital Library
- 5.K. Roy and S. Prasad, "Circuit activity based logic synthesis for low power reliable operations," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 4, pp. 503-513, Dec. 1993.Google ScholarDigital Library
- 6.L. Benini and G. De Micheli, "State assignment for low power dissipation," in CICC, Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 136-139, May 1994.Google ScholarCross Ref
- 7.B. Suessmith and G. Paap III, "PowerPC 603 microprocessor power management," Communications of the A CM, no. 6, pp. 43-46, June 1994. Google ScholarDigital Library
- 8.K. Trivedi. Probability and statistics with reliability, queuing and computer science applications. Prentice-Hall, 1982. Google ScholarDigital Library
- 9.G. Hachtel, E. Macii, A. Pardo and F. Somenzi "Symbolic algorithms to calculate Steady-State probabilities of a finite state machine," in Proc. of IEEE European Design and Test Conf., pp. 214-218, Feb. 1994.Google Scholar
- 10.J. Schutz, "A 3.3V 0.6ttm BiCMOS superscalar microprocessor," in IEEE International Solid-State Circuits Conference, pp. 202-203, Feb. 1994.Google Scholar
- 11.J. Hartmanis and H. Stearns, Algebraic Structure Theory of Sequential Machines. Prentice-Hall, 1966. Google ScholarDigital Library
- 12.E. Sentovich, et al., "Sequential circuit design using synthesis and optimization," in ICCD, Proceedings of the International Conference on Computer Design, pp. 328-333, Oct. 1992. Google ScholarDigital Library
- 13.F. Mailhot and G. De Micheli, "Algorithms for technology mapping based on binary decision diagrams and on Boolean operations," IEEE Transactions on CAD/ICAS, pp. 599-620, May 1993.Google Scholar
- 14.G. De Micheli. Synthesis and optimization of digital circuits. McGraw-Hill, 1994. Google ScholarDigital Library
- 15.O. Coudert and C. Madre, "Implicit and incremental computation of primes and essential primes of Boolean functions," in DAC, Proceedings of the Design Automation Conference, pp. 36-39, June 1992. Google ScholarDigital Library
- 16.R. Marculescu, D. Marculescu and M. Pedram, "Switching activity analysis considering spatiotemporal correlations," in ICCAD, Proceedings of the International Conference on Computer-Aided Design, pp. 294-299, Nov. 1994 Google ScholarDigital Library
- 17.B. Lin and A. R. Newton, "Synthesis of multiple-level logic from symbolic high-level description languages," in Proc. of IEEE Int. Conf. On Computer Design, pp. 187-196, Aug. 1989.Google Scholar
- 18.A. Salz and M. Horowitz, "IRSIM: an incremental MOS switch-level simulator," in DA C, Proceedings of the Design Automation Conference, pp. 173-178, June 1989. Google ScholarDigital Library
Index Terms
- Transformation and synthesis of FSMs for low-power gated-clock implementation
Recommendations
Clock Gated Low Power Memory Implementation on Virtex-6 FPGA
CICN '13: Proceedings of the 2013 5th International Conference on Computational Intelligence and Communication NetworksIn this work, Virtex-6 is Target 40nm FPGA Device. Xilinx ISE 14.1 is an ISE Design tool. RAM is a target design. Clock Gating is a technique which decreases clock power but increases Logic Power due to added Logic in Design. Irrespective of increase in ...
Logic transformation for low-power synthesis
In this article we present a new approach to the problem of local logic transformation for reducing power dissipation in logic circuits. The proposed approach overcomes one of the critical limitations common to the previous approaches of local logic ...
Automatic synthesis of low-power gated-clock finite-state machines
The automatic synthesis of low power finite-state machines (FSM's) with gated clocks relies on efficient algorithms for synthesis and optimization of dedicated clock-stopping circuitry. We describe a new transformation for incompletely specified Mealy-...
Comments