skip to main content
research-article

Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling

Published:01 September 2012Publication History
Skip Abstract Section

Abstract

This article proposes a novel approach to cryptosystem design to prevent power analysis attacks. Such attacks infer program behavior by continuously monitoring the power supply current going into the processor core. They form an important class of security attacks. Our approach is based on dynamic voltage and frequency scaling (DVFS), which hides processor state to make it harder for an attacker to gain access to a secure system. Three designs are studied to test the efficacy of the DVFS method against power analysis attacks. The advanced realization of our cryptosystem is presented which achieves enough high power and time trace entropies to block various kinds of power analysis attacks in the DES algorithm. We observed 27% energy reduction and 16% time overhead in these algorithms. Finally, DVFS hardness analysis is presented.

References

  1. Benini, L., Galati, A., Macii, A., Macii, E., and Poncino, M. 2003a. Energy-efficient data scrambling on memory-processor interfaces. In Proceedings of the International Symposium on Low Power Electronics and Design. 26--29. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Benini, L., Macii, A., Macii, E., Omerbegovic, E., Poncino, M., and Pro, F. 2003b. Energy-aware design techniques for differential power analysis protection. In Proceedings of the Design Automation Conference. 36--41. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Boneh, D., DeMillo, R., and Lipton, R. 2001. On the importance of eliminating errors in cryptographic computations. J. Cryptol. 14, 2, 101--119.Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Burd, T., Pering, T., Stratakos, A., and Brodersen, R. 2000. A dynamic voltage scaled microprocessor system. IEEE Trans. Syst. Sci. Cybern. 35, 11, 1571--1580.Google ScholarGoogle Scholar
  5. Burd, T. D. and Brodersen, R. 2000. Design issues for dynamic voltage scaling. 9--14. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Burd, T. D., Pering, T. A., Stratakos, A. J., and Brodersen, R. W. 2002. A dynamic voltage scaled microprocessor system. IEEE J. Solid-State Circ. 35, 11, 1571--1580.Google ScholarGoogle ScholarCross RefCross Ref
  7. Chevallier-Mames, B., Ciet, M., and Joye, M. 2004. Low-cost solutions for preventing simple side-channel analysis: Side-channel atomicity. IEEE Trans. Comput. 53, 6, 760--768. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Choi, K., Soma, R., and Pedram, M. 2004. Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding. In Proceedings of the 41st Annual Design Automation Conference. 544--549. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Coron, J. 1999. Resistance against differential power analysis for elliptic curve cryptosystems. In Proceedings of the International Workshop on Cryptographic Hardware & Embedded Systems. 292--302. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Ghiasi, S., Casmira, J., and Grunwald, D. 2000. Using IPC variation in workload with externally specified rates to reduce power consumption. In Proceedings of the Workshop on Complexity-Effective Design.Google ScholarGoogle Scholar
  11. Giancane, L., Marietti, P., Olivieri, M., Scotti, G., and Trifiletti, A. 2008. A new dynamic differential logic style as a countermeasure to power analysis attacks. In Proceedings of the International Conference on Electronics, Circuits and Systems. 364--367.Google ScholarGoogle Scholar
  12. Goubin, L. and Patarin, J. 1999. DES and differential power analysis - the duplication method. In Proceedings of the International Workshop on Cryptographic Hardware & Embedded Systems. 158--172. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Guiley, S., Sauvage, L., Hoogvorst, P., Pacalet, R., Bertonian, G. M., and Chaudhuri, S. 2008. Security evaluation of WDDL and SecLib countermeasures against power attacks. IEEE Trans. Comput. 57, 11, 1482--1497. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Khatibzadeh, A. and Gebotys, C. 2007. Enhanced current-balanced logic (ECBL): An area efficient solution to secure smart cards against differential power attack. In Proceedings of the International Conference on Information Technology. 898--899. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Kocher, P. 1996. Timing attacks on implementations of Diffe-Hellman, RSA, DSS and other systems. In Proceedings of the Conference on Advances in Cryptology. 104--113. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Kocher, P., Jaffe, J., and Jun, B. 1999. Differential power analysis. In Proceedings of the Conference on Advances in Cryptology. 388--397. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Kocher, P., Lee, R., McGraw, G., Raghunathan, A., and Ravi, S. 2004. Security as a new dimension in embedded system design. In Proceedings of the 41st Design Automation Conference (DAC’04). 753--760. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Kömmerling, O. and Kuhn, M. G. 1999. Design principles for tamper-resistant smartcard processors. In Proceedings of the USENIX Workshop on Smartcard Technology. 1--12. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Koopman, P. 2004. Embedded system security. IEEE Computer 37, 2 (July), 95--97. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Lorch, J. R. and Smith, A. J. 2004. PACE: A new approach to dynamic voltage scaling. IEEE Trans. Comput. 53, 7, 856--869. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Luo, J., Jha, N. K., and Peh, L. 2007. Simultaneous dynamic voltage scaling of processors and communication links in real-time distributed embedded systems. IEEE Trans. VLSI Syst. 15, 4, 427--437. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Moore, S., Anderson, R., Cunningham, P., Mullins, R., and Taylor, G. 2002. Improving smart card security using self-timed circuits. In Proceedings of the International Symposium on Asynchronous Circuits & Systems. 211--218. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Narayanan, V., Kandemir, M., Irwin, M. J., Kim, H. S., and Ye, W. 2000. Energy-driven integrated hardware-software optimizations using SimplePower. In Proceedings of the Annual International Symposium on Computer Architecture. 95--106. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Nowka, K. J., Carpenter, G. D., MacDonald, E. W., Ngo, H. C., Brock, B. C., Ishii, K. I., Nguyen, T. Y., and Burns, J. L. 2002. A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling. IEEE J. Solid-State Circ. 37, 11, 1441--1447.Google ScholarGoogle ScholarCross RefCross Ref
  25. Quisquater, J. J. and Samyde, D. 2001. Electromagnetic analysis (EMA): Measures and counter-measures for smart cards. In Proceedings of the Conference on Research in Smart Cards. 200--210. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Quisquater, J. J. and Samyde, D. 2002. Side-channel cryptanalysis. In Proceedings of Securité de la Communication sur Internet (SECI’02). 179--184.Google ScholarGoogle Scholar
  27. Ratanpal, G. B., Williams, R. D., and Blalock, T. N. 2004. An on-chip signal suppression countermeasure to power analysis attacks. IEEE Trans. Dependable Secure Comput. 1, 3, 179--189. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Ravi, S., Raghunathan, A., and Chakradhar, S. 2003. Embedding security in wireless embedded systems. In Proceedings of the 16th International Conference on VLSI Design. 269--270. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Real, D., Clediere, J., Canovas, C., Drissi, M., and Valette, F. 2008. Defeating classical hardware countermeasures: A new processing for side channel analysis. In Proceedings of the Conference on Design, Automation and Test in Europe. 1274--1279. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Regazzoni, F., Eisenbarth, T., Grobschadl, J., Breveglieri, L., Ienne, P., Koren, I., and Paar, C. 2007. Power attacks resistance of cryptographic S-boxes with added error detection circuits. In Proceedings of the International Symposium on Defect & Fault Tolerance in VLSI Systems. 508--516. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. Rohatgi, P. 2010. Protecting FPGAs from power analysis. Tech. rep., Cryptography Research Inc.Google ScholarGoogle Scholar
  32. Saputra, H., Narayanan, V., Kandemir, M., Irwin, M. J., Brooks, R., and Zhang, S. K. W. 2003. Masking the energy behavior of DES encryption. IEE Proc. Comput. Digital Techn. 84--89.Google ScholarGoogle Scholar
  33. Schneier, B. 1996. Applied Cryptography, Protocols, Algorithms, and Source Code in C. John Wiley, New York, NY. Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. Sen, S., Hossain, S. I., Islam, K., Chowdhuri, D. R., and Chaudhuri, P. P. 2003. Cryptosystem designed for embedded system security. In Proceedings of the 16th International Conference on VLSI Design. 271--276. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. Tiri, K. and Verbauwhede, I. 2003. Securing encryption algorithms against DPA at the logic level: next generation smart card technology. In Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems. 125--136.Google ScholarGoogle Scholar
  36. Wagner, D. and Waddle, J. 2004. Towards efficient second-order power analysis. In Proceedings of the International Workshop on Cryptographic Hardware & Embedded Systems. 1--15.Google ScholarGoogle Scholar
  37. Xian, C., Lu, Y. H., and Li, Z. 2008. Dynamic voltage scaling for multitasking real-time systems with uncertain execution time. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 27, 8, 1467--1478. Google ScholarGoogle ScholarDigital LibraryDigital Library
  38. Zhai, B., Blaauw, D., Sylvester, D., and Flautner, K. 2004. Theoretical and practical limits of dynamic voltage scaling. In Proceedings of the 41st Annual Design Automation Conference. 868--873. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling

            Recommendations

            Comments

            Login options

            Check if you have access through your login credentials or your institution to get full access on this article.

            Sign in

            Full Access

            • Published in

              cover image ACM Transactions on Embedded Computing Systems
              ACM Transactions on Embedded Computing Systems  Volume 11, Issue 3
              September 2012
              274 pages
              ISSN:1539-9087
              EISSN:1558-3465
              DOI:10.1145/2345770
              Issue’s Table of Contents

              Copyright © 2012 ACM

              Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

              Publisher

              Association for Computing Machinery

              New York, NY, United States

              Publication History

              • Published: 1 September 2012
              • Accepted: 1 July 2010
              • Revised: 1 May 2010
              • Received: 1 June 2009
              Published in tecs Volume 11, Issue 3

              Permissions

              Request permissions about this article.

              Request Permissions

              Check for updates

              Qualifiers

              • research-article
              • Research
              • Refereed

            PDF Format

            View or Download as a PDF file.

            PDF

            eReader

            View online with eReader.

            eReader