skip to main content
10.1145/240518.240584acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
Article
Free Access

Scheduling techniques to enable power management

Published:01 June 1996Publication History
First page image

References

  1. 1.M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou. Precomputation-Based Sequential Logic Optimization for Low Power. IEEE Transactions on VLSI Systems, 2(4):426-436, December 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. 2.A. Chandrakasan, M. Potkonjak, J. Rabaey, and R. Broderson. HYPER-LP: A System for Power Minimization Using Architectural Transformations. In Proc. of the ICCAD, pages 300-303, November 1992. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. 3.Anantha Chandrakasan and Robert Brodersen. Low Power Digital CMOS Design. Kluwer Academic Publishers, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. 4.E Hilfinger. A High-level Language and Silicon Compiler for Digital Signal Processing. In Proc. of the Custom Integrated Circuits Conference, pages 213-216, May 1985.Google ScholarGoogle Scholar
  5. 5.H. Juan, V. Chaiyakul, and D. Gajski. Condition Graphs for High-Quality Behvioral Synthesis. In Proc. of the ICCAD, pages 170-174, November 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. 6.J. Monteiro, J. Rinderknecht, S. Devadas, and A. Ghosh. Optimization of Combinational and Sequential Logic Circuits for Low Power Using Precomputation. In Proc. of the Chapel Hill Conf. on Advanced Research on VLSI, pages 430-444, March 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. 7.J. Rabaey, C. Chu, E Hoang, and M. Potkonjak. Fast Prototyping of Datapath-Intensive Architectures. IEEE Design and Test, 8(2):40-51, June 1991. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. 8.A. Raghunathan and N. Jha. Behavioral Synthesis for Low Power. In Proc. of the ICCD, pages 318-322, October 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. 9.V. Tiwari, E Ashar, and S. Malik. Guarded evaluation: Pushing power management to logic synthesis/design. In International Symposium on Low Power Design, pages 221-226, April 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Scheduling techniques to enable power management

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in
    • Published in

      cover image ACM Conferences
      DAC '96: Proceedings of the 33rd annual Design Automation Conference
      June 1996
      839 pages
      ISBN:0897917790
      DOI:10.1145/240518

      Copyright © 1996 ACM

      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 1 June 1996

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • Article

      Acceptance Rates

      DAC '96 Paper Acceptance Rate142of377submissions,38%Overall Acceptance Rate1,770of5,499submissions,32%

      Upcoming Conference

      DAC '24
      61st ACM/IEEE Design Automation Conference
      June 23 - 27, 2024
      San Francisco , CA , USA

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader