- 1.M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou. Precomputation-Based Sequential Logic Optimization for Low Power. IEEE Transactions on VLSI Systems, 2(4):426-436, December 1994. Google ScholarDigital Library
- 2.A. Chandrakasan, M. Potkonjak, J. Rabaey, and R. Broderson. HYPER-LP: A System for Power Minimization Using Architectural Transformations. In Proc. of the ICCAD, pages 300-303, November 1992. Google ScholarDigital Library
- 3.Anantha Chandrakasan and Robert Brodersen. Low Power Digital CMOS Design. Kluwer Academic Publishers, 1995. Google ScholarDigital Library
- 4.E Hilfinger. A High-level Language and Silicon Compiler for Digital Signal Processing. In Proc. of the Custom Integrated Circuits Conference, pages 213-216, May 1985.Google Scholar
- 5.H. Juan, V. Chaiyakul, and D. Gajski. Condition Graphs for High-Quality Behvioral Synthesis. In Proc. of the ICCAD, pages 170-174, November 1994. Google ScholarDigital Library
- 6.J. Monteiro, J. Rinderknecht, S. Devadas, and A. Ghosh. Optimization of Combinational and Sequential Logic Circuits for Low Power Using Precomputation. In Proc. of the Chapel Hill Conf. on Advanced Research on VLSI, pages 430-444, March 1995. Google ScholarDigital Library
- 7.J. Rabaey, C. Chu, E Hoang, and M. Potkonjak. Fast Prototyping of Datapath-Intensive Architectures. IEEE Design and Test, 8(2):40-51, June 1991. Google ScholarDigital Library
- 8.A. Raghunathan and N. Jha. Behavioral Synthesis for Low Power. In Proc. of the ICCD, pages 318-322, October 1994. Google ScholarDigital Library
- 9.V. Tiwari, E Ashar, and S. Malik. Guarded evaluation: Pushing power management to logic synthesis/design. In International Symposium on Low Power Design, pages 221-226, April 1995. Google ScholarDigital Library
Index Terms
- Scheduling techniques to enable power management
Recommendations
Demand-aware power management for power-constrained HPC systems
CCGRID '16: Proceedings of the 16th IEEE/ACM International Symposium on Cluster, Cloud, and Grid ComputingAs limited power budget is becoming one of the most crucial challenges in developing supercomputer systems, hardware overprovisioning which installs larger number of nodes beyond the limitations of the power constraint determined by Thermal Design Power ...
Low power scheduling of DAGs to minimize finish times
HiPC'06: Proceedings of the 13th international conference on High Performance ComputingWe propose a schedule named Low Power Heterogeneous Makespan (LPHM) that attempts to minimize makespan as well as power consumption in the execution of any directed acyclic task graph on heterogeneous processors. We combine the techniques of ...
Parallel job scheduling for power constrained HPC systems
Power has become the primary constraint in high performance computing. Traditionally, parallel job scheduling policies have been designed to improve certain job performance metrics when scheduling parallel workloads on a system with a given number of ...
Comments