Behnam Ghavami
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Abstract
Carbon Nanotube Field Effect Transistors (CNFETs) show great promise as extensions to silicon CMOS. However, CNFET-based circuits will face great fabrication challenges that will translate into important parameter variations and decreased reliability. Hence, asynchronous logic, which is intrinsically more robust to variability, seems an ideal and perhaps unavoidable choice for digital circuits in CNFET technology. This article presents the results on the design and analysis of a CNFET-based implementation of an asynchronous circuit primitive: the Muller C-element. Using a CNFET SPICE model, we evaluate the robustness of CNFET-based C-element in the presence of CNT fabrication-related nonidealities. We investigate a quantitative evaluation of how timing variability impacts the functionality of a C-element and then, extract the necessary delay constraints of the C-element circuit from the signal transition graph specification. Considering the large degrees of spatial correlation observed between the CNFETs fabricated on directionally grown CNTs, a layout technique is exploited to overcome the robustness challenges of a CNFET-based C-element. Extensive Monte Carlo simulations on the proposed technique have demonstrated the effectiveness of the proposed CNFET-based C-element by improving approximately 50X in its robustness in expense of 65% area, 47% delay, and 56% power consumption overheads. Experimental results indicate that implementation of some CNFET-based Quasi Delay Insensitive (QDI) benchmark circuits using the proposed C-element results in significant robustness improvement with negligible power and throughput overheads. As a promising step toward CNFET-based giga-scale integrated circuits, this article shows that the asynchronous logic is an effective approach to design robust integrated circuits in CNFET technology with inherent extreme physical variations.
- Ashraf, R., Chrzanowska-Jeske, M., and Narendra, S. G. 2010. Functional yield estimation of carbon nanotube based logic gates in the presence of defects. IEEE Trans. Nanotechnol. 29, 6, 687--700. Google Scholar
Digital Library
- Beerel, P. A., Ozdag, R. O., and Ferretti, M. 2010. A Designer’s Guide To Asynchronous VLSI. Cambridge University Press. Google ScholarDigital Library
- Boddapati, H., Naregalkar, A., and Raju, B. L. 2011. High speed power efficient asynchronous adders. In Proceedings of the International Conference and Workshop on Emerging Trends in Technology. 27--32.Google Scholar
- Brzozowski, J. A. and Raahemifar, K. 1995. Testing c-elements is not elementary. In Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies. 150--159. Google ScholarDigital Library
- Brzozowski, J. A. and Seger, C. J. H. 1995. Asynchronous Circuits. Springer.Google Scholar
- Chakraborty, R. S. and Bhunia, S., 2008. Micropipeline-based asynchronous design methodology for robust system design using nanoscale crossbar. In Proceedings of the 9th International Symposium on Quality Electronic Design. 697--701. Google ScholarDigital Library
- Chen, T. C. 2006. Overcoming research challenges for CMOS scaling: industry directions. In Proceedings of the IEEE International Conference on Solid-State and Integrated Circuit Technology. 4--7.Google ScholarCross Ref
- Cui, Y., Zhong, Z., Wang, D., Wang, W. U., and Lieber, C. M. 2003. High performance silicon nanowire field effect transistors. Nano Lett. 3, 2, 149--152.Google ScholarCross Ref
- Deng, J. and Wong, H. S. P. 2007. A compact spice model for carbon-nanotube field-effect transistors including nonidealities and its application---part i: Model of the intrinsic channel region. IEEE Trans. Electron. Devices 54, 12, 3186--3194.Google ScholarCross Ref
- Efthymiou, A. 2010. Initialization-based test pattern generation for asynchronous circuits. IEEE Trans. VLSI. Syst. 18, 4, 591--601. Google ScholarDigital Library
- Furber, S. B. and Day, P. 1996. Four-phase micropipeline latch control circuits. IEEE Trans. VLSI Syst. 4, 2, 247--253. Google ScholarDigital Library
- Ghavami, B. and Pedram, H. 2009. High performance asynchronous design flow using a novel static performance analysis method. Comput. Electr. Eng. 35, 6, 920--941. Google ScholarDigital Library
- Ghavami, B., Pedram, H., and Najibi, M. 2008. An EDA tool for implementation of low power and secure crypto-chips. Comput. Electr. Eng. 35, 2, 244--257. Google ScholarDigital Library
- Ghavami, B., Zarandi, H. R., Salarpour, A., and Pedram, H. 2009. Diagnosis of faults in template-based asynchronous circuits. In Proceedings of the 11th international Conference on System-on-Chip. 38--41. Google ScholarDigital Library
- Ghavami, B., Pedram, H., and Niknahad, M. 2010. An efficient energy estimation methodology for quasi delay insensitive template-based asynchronous circuits. J. Low Power Electron. 6, 1, 1--9.Google ScholarCross Ref
- Ghavami, B., Raji, M., and Pedram, H. 2011a. Timing yield estimation of carbon nanotube-based digital circuits in the presence of nanotube density variation and metallic-nanotubes. In Proceedings of the 12th International Symposium on Quality Electronic Design. 1--8.Google Scholar
- Ghavami B., Raji, M., and Pedram, H. 2011b. A statistical-based material and process guidelines for design of carbon nanotube field-effect transistors in gigascale integrated circuits. Nanotechnol. 26, 22, 34, 345706.Google Scholar
- Gill, G., Gupta, V., and Singh, M. 2008. Performance estimation and slack matching for pipelined asynchronous architectures with choice. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 449--456. Google ScholarDigital Library
- Gupta, P. and Kahng, A. B. 2003. Manufacturing-aware physical design. Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 681--689. Google ScholarDigital Library
- Haron, N. Z. and Hamdioui, S. 2008. Why is CMOS scaling coming to an end? In Proceedings of the 3rd IEEE International Design and Test Workshop. 98--103.Google Scholar
- Haselman, M. and Hauck, S. 2009. The future of integrated circuits: A survey of nanoelectronics. Proc. IEEE 98, 1, 11--38.Google ScholarCross Ref
- Hatami, S., Abrishami, H., and Pedram, M. 2008. Statistical timing analysis of flip-flops considering codependent setup and hold times. In Proceedings of the 18th ACM Great Lakes symposium on VLSI. 101--106. Google ScholarDigital Library
- International Technology Roadmap for Semiconductor 2007 Edition Executive Summary. http://www.itrs.netiLinks/2007ITRS/ExecSum2007.pdf.Google Scholar
- Iwai, H. 2004. CMOS scaling for sub-90 nm to sub-l0 nm. In Proceedings of the 3rd IEEE International Conference on VLSI Design. 30--35. Google ScholarDigital Library
- Javey, A., Guo, J., Farmer, D. B., Wang, Q., Wang, D., Gordon, R. G., Lundstrom, M., and Dai, H. 2003. Carbon nanotube field-effect transistors with integrated ohmic contacts and high-k gate dielectrics. Nano Lett. 4, 447--450.Google ScholarCross Ref
- Jiang, H. and Sapatnekar, S. S. 2002. A timing-constrained simultaneous global routing algorithm. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 21, 9, 1025--1036. Google ScholarDigital Library
- Kang, S. J., Kocabas, C., Ozel, T., Shim, M. , Pimparkar, N., Alam, M. A., Rotkin, S. V., and Rogers, J. A. 2007. High-performance electronics using dense, perfectly aligned arrays of single-walled carbon nanotubes. Nat. Nanotechnol. 2, 4, 230--236.Google ScholarCross Ref
- Lavagno, L., Keutzer, K., and Sangiovanni-Vincentelli, A. L. 1995. Synthesis of hazard-free asynchronous circuits with bounded interconnect delays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14, 1, 61--86. Google ScholarDigital Library
- Lin, C. and Zhou, H. 2007. Clock skew scheduling with delay padding for prescribed skew domains. In Proceedings of the Asia and South Pacific Design Automation Conference. 541--546.Google Scholar
- Lin, A., Patil, N., Wei, H., Mitra, S., and Wong, H. S. P. 2009. ACCNT: A metallic-cnt-tolerant design methodology for carbon-nanotube VLSI: Concepts and experimental demonstration. IEEE Trans. Electron Devices 56, 12, 2969--2978.Google ScholarCross Ref
- Liu, J. H., Tsai, M. F., Chen, L., and Chen, C. C. P. 2008. Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications. In Proceedings of the 45th Annual Design Automation Conference. 694--697. Google ScholarDigital Library
- Liu, J. H., Tsai, M. F., Chen, L., and Chen, C. C. P. 2010. Accurate and analytical statistical spatial correlation modeling based on singular value decomposition for VLSI DFM applications. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 29, 4, 580--589. Google ScholarDigital Library
- Martel, R., Schmidt, T., Shea, H. R., Hertel, T., and Avouris, P. 1998. Single- and multi-wall carbon nanotube field-effect transistors. Appl. Phys. Lett. 73, 17, 2447.Google ScholarCross Ref
- Martin, A. J., 1990. The limitations to delay-insensitivity in asynchronous circuits. In Proceedings of the 6th MIT Conference on Advanced Research in VLSI. MIT Press. Google ScholarDigital Library
- Martin, A. J. and Prakash, P. 2008. Asynchronous nano-electronics: preliminary investigation. In Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems. 58--68. Google ScholarDigital Library
- McCluskey, E. J. 1963. Fundamental mode and pulse mode sequential circuits. In Proceedings of the IFIP Congress. 725--730.Google Scholar
- Miller, R. E. 1965. Sequential circuits and machines. In Switching Theory 2, Wiley.Google Scholar
- Murata, T. 1989. Petri Nets: Properties, analysis and applications. Proc. IEEE 77, 4, 541--580.Google ScholarCross Ref
- Najm, F. N., Menezes, N., and Ferzli, I. A. 2007. A yield model for integrated circuits and its application to statistical timing analysis. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 26, 3, 574--591. Google ScholarDigital Library
- Ozdag, R. O. and Beerel, P. A. 2002. High-speed qdi asynchronous pipelines. In Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems. 13--22. Google ScholarDigital Library
- Patil, N., Deng, J., Wong, H. S. P., and Mitra, S. 2007. Automated design of misaligned-carbon-nanotubeimmune circuits. In Proceedings of the IEEE/ACM Design Automation Conference. 958--961. Google ScholarDigital Library
- Patil, N., Deng, J., Mitra, S., and Wong, H. S. P. 2009. Circuit-level performance benchmarking and scalability analysis of carbon nanotube transistor circuits. IEEE Trans. Nanotechnol. 8, 1, 37--45. Google ScholarDigital Library
- Rahbaran, B. and Steininger, A. 2009. Is asynchronous logic more robust than synchronous logic? IEEE Trans. Dependable Secure Comput. 6, 4, 282--294. Google ScholarDigital Library
- Raji, M., Ghavami, B., Pedram, H., and Zarandi, H. R. 2010. Process variation-aware performance analysis of asynchronous circuits. Microelectron. J. 41, 2--3, 99--108. Google ScholarDigital Library
- Raychowdhury, A., Keshavarzi, A., Kurtin, J., De, V., and Roy, K. 2006. Carbon nanotube field-effect transistors for high-performance digital circuits-dc analysis and modeling toward optimum transistor structure. IEEE Trans. Electron Devices 53, 11, 2711--2717.Google ScholarCross Ref
- Reddy, D., Register, L. F., Carpenter, G. D., and Banerjee, S. K. 2011. Graphene field-effect transistors. J. Phys. D: Appl. Phys. 44, 313001.Google ScholarCross Ref
- Ross, S. A. 2001. A First Course in Probability 6th Ed. Prentice Hall.Google Scholar
- Shams, M., Ebergen, J. C., and Elmasry, M. I. 1998. Modeling and comparing CMOS implementations of the celement. IEEE Trans. VLSI Syst. 6, 4, 563--567. Google ScholarDigital Library
- Skotnicki, T., Hutchby, J. A., King, T., Wong, H. S. P., and Boeuf, F. 2005. The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits Devices Mag. 21,1, 16--26.Google ScholarCross Ref
- Sparso, J. and Furber, S. 2001. Principles of Asynchronous Circuit: A Systems Perspective. Kluwer. Google ScholarDigital Library
- Wang, X., Kwiatkowska, M., Theodoropoulos, G., and Zhang, Q. 2006. Opportunities and challenges in process-algebraic verification of asynchronous circuit designs. Electron. Notes Theor. Comput. Sci. 146, 2, 189--206. Google ScholarDigital Library
- Wong, H. S. P., Appenzeller, J., Derycke, V., Martel, R., Wind, S., and Avouris, P. 2003. Carbon nanotube field effect transistors -- fabrication, device physics, and circuit implications. In Proceedings of the IEEE International Solid State Circuits Conference. 370--371.Google Scholar
- Zhang, J., Patil, N., Hazeghi, A., and Mitra, S. 2009a. Carbon nanotube circuits in the presence of carbon nanotube density variations. In Proceedings of the IEEE/ACM Design Automation Conference. 71--76. Google ScholarDigital Library
- Zhang, J., Patil, N., and Mitra, S. 2009b. Probabilistic analysis and design of metallic-carbon-nanotubetolerant digital logic circuits. IEEE Trans. Comput.-Aided Des. 28, 9, 1307--1320. Google ScholarDigital Library
- Zhang, J., Patil, N., Lin, A., Wong, H. S. P., and Mitra, S. 2010a. Carbon nanotube circuits: Living with imperfections and variations. In Proceedings of the IEEE/ACM Design Automation Conference. 1159--1164. Google ScholarDigital Library
Index Terms
- Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
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