Abstract
Power consumption has become a very important consideration during integrated circuit (IC) design and test. During test, it can far exceed the values reached during normal operation and, thus, lead to temperatures above the allowed threshold. Without appropriate temperature reduction, permanent damage may be caused to the IC or invalid test results may be obtained. FinFET is a double-gate field-effect transistor (DG-FET) that was introduced commercially in 2012. Due to the vertical nature of FinFETs and, hence, weaker ability to dissipate heat, this problem is likely to get worse for FinFET circuits. Another technology rapidly gaining popularity is 3D IC integration. Unfortunately, the compact nature of a multidie 3D IC is likely to aggravate the temperature-during-test problem even further. Hence, before temperature-aware test methodologies can be developed, it is important to thermally analyze both FinFET and 3D circuits under test.
In this article, we present a methodology for thermal characterization of various test techniques, such as scan and built-in self-test (BIST), for FinFET and 3D ICs. FinFET thermal characterization makes use of a FinFET standard cell library that is characterized with the help of the University of Florida double-gate (UFDG) SPICE model. Thermal profiles for circuits under test are produced by ISAC2 from University of Colorado for FinFET circuits and HotSpot from University of Virginia for 3D ICs. Experimental results indicate that high temperatures result under BIST and much less often under scan, and that both power consumption and test application time should be reduced to lower the temperature of circuits under test, just reducing the power consumption is not enough.
- Allec, N., Hassan, Z., Shang, L., Dick, R. P., and Yang, R. 2008. Thermalscope: Multi-scale thermal analysis for nanometer-scale integrated circuits. In Proceedings of the International Conference on Computer-Aided Design. 603--610. Google ScholarDigital Library
- Bhoj, A. N. and Jha, N. K. 2010. Gated-diode FinFET DRAMs: Device and circuit design-considerations. J. Emerg. Technol. Comput. Syst. 6, 4, 12:1--12:32. Google ScholarDigital Library
- Bhunia, S., Mahmoodi, H., Ghosh, D., Mukhopadhyay, S., and Roy, K. 2005. Low-power scan design using first-level supply gating. IEEE Trans. VLSI Syst. 13, 3, 384--395. Google ScholarDigital Library
- Bild, D. R., Misra, S., Chantemy, T., Kumar, P., Dick, R. P., Huy, X. S., Shang, L., and Choudhary, A. 2008. Temperature-aware test scheduling for multiprocessor systems-on-chip. In Proceedings of the International Conference on Computer-Aided Design. 59--66. Google ScholarDigital Library
- Butler, K. M., Saxena, J., Jain, A., Fryars, T., Lewis, J., and Hetherington, G. 2004. Minimizing power consumption in scan testing: Pattern generation and DFT techniques. In Proceedings of the International Test Conference. 355--364. Google ScholarDigital Library
- Chiang, M.-H., Kim, K., Tretz, C., and Chuang, C.-T. 2005. Novel high-density low-power logic circuit techniques using DG devices. IEEE Trans. Electron Devices 52, 10, 2339--2342.Google ScholarCross Ref
- Chiu, M.-H. and Li, J. C.-M. 2005. Jump scan: A DFT technique for low power testing. In Proceedings of the VLSI Test Symposium. 277--282. Google ScholarDigital Library
- Cho, K. Y., Mitra, S., and McCluskey, E. J. 2007. California scan architecture for high quality and low power testing. In Proceedings of the International Test Conference. 1--10.Google Scholar
- Choi, J. H., Murthy, J., and Roy, K. 2007. The effect of process variation on device temperature in FinFET circuits. In Proceedings of the International Conference on Computer Aided Design. 747--751. Google ScholarDigital Library
- Czysz, D., Kassab, M., Lin, X., Mrugalski, G., Rajski, J., and Tyszer, J. 2008. Low power scan shift and capture in the EDT environment. In Proceedings of the International Test Conference. 1--10.Google Scholar
- Datta, A., Goel, A., Cakici, R. T., Mahmoodi, H., Lekshmanan, D., and Roy, K. 2007. Modeling and circuit synthesis for independently controlled double gate FinFET devices. IEEE Trans. Comput.-Aided Des. 26, 11, 1957--1966. Google ScholarDigital Library
- Fossum, J. G., Ge, L., Chiang, M.-H., Trivedi, V. P., Chowdhury, M. M., Mathew, L., Workman, G. O., and Nguyen, B.-Y. 2004. A process/physics-based compact model for nonclassical CMOS device and circuit design. Solid-State Electron. 8, 919--926.Google ScholarCross Ref
- Girard, P. 2002. Survey of low-power testing of VLSI circuits. IEEE Des. Test Comput. 19, 3, 80--90. Google ScholarDigital Library
- Girard, P., Landrault, C., Pravossoudovitch, S., and Severac, D. 1998. Reducing power consumption during test application by test vector ordering. In Proceedings of the International Symposium on Circuits and Systems. Vol. 2, 296--299.Google Scholar
- Giri, C., Choudhary, P. K., and Chattopadhyay, S. 2007. Scan architecture modification with test vector reordering for test power reduction. In Proceedings of the International Symposium on Integrated Circuits. 449--452.Google Scholar
- Gu, J., Keane, J., Sapatnekar, S., and Kim, C. H. 2008. Statistical leakage estimation of double gate FinFET devices considering the width quantization property. IEEE Trans. VLSI Syst. 16, 2, 206--209. Google ScholarDigital Library
- Huang, W., Ghosh, S., Velusamy, S., Sankaranarayanan, K., Skadron, K., and Stan, M. R. 2006. HotSpot: A compact thermal modeling methodology for early-stage VLSI design. IEEE Trans. VLSI Syst. 14, 5, 501--513. Google ScholarDigital Library
- Hung, W., Addo-Quaye, C., Theocharides, T., Xie, Y., Vijaykrishnan, N., and Irwin, M. J. 2004. Thermal-aware IP virtualization and placement for networks-on-chip architecture. In Proceedings of the International Conference on Computer Design. 430--437. Google ScholarDigital Library
- Jha, N. K. and Gupta, S. 2003. Testing of Digital Systems. Cambridge University Press, Cambridge, UK. Google ScholarDigital Library
- Kumar, A., Minch, B. A., and Tiwari, S. 2004. Low voltage and performance tunable CMOS circuit design using independently driven double gate MOSFETs. In Proceedings of the International SOI Conference. 119--121.Google Scholar
- Li, W., Reddy, S. M., and Pomeranz, I. 2005. On reducing peak current and power during test. In Proceedings of the Annual Symposium on VLSI. 156--161. Google ScholarDigital Library
- Lin, X., Pomeranz, I., and Reddy, S. M. 1998. MIX: A test generation system for synchronous sequential circuits. In Proceedings of the International Conference on VLSI Design. 456--463. Google ScholarDigital Library
- Liu, C., Iyengar, V., and Pradhan, D. K. 2006. Thermal-aware testing of network-on-chip using multiple-frequency clocking. In Proceedings of the VLSI Test Symposium. 46--51. Google ScholarDigital Library
- Liu, Y., Dick, R. P., Shang, L., and Yang, H. 2007. Accurate temperature-dependent integrated circuit leakage power estimation is easy. In Proceedings of the Design, Automation and Test in Europe Conference. Google ScholarDigital Library
- Mishra, P. and Jha, N. K. 2010. Low-power FinFET circuit synthesis using surface orientation optimization. In Proceedings of the Design, Automation and Test in Europe Conference. 311--314. Google ScholarDigital Library
- Mishra, P., Muttreja, A., and Jha, N. K. 2009. Low-power FinFET circuit synthesis using multiple supply and threshold voltages. J. Emerg. Technol. Comput. Syst. 5, 7:1--7:23. Google ScholarDigital Library
- Mishra, P., Bhoj, A. N., and Jha, N. K. 2010. Die-level leakage power analysis of FinFET circuits considering process variations. In Proceedings of the International Symposium on Quality Electronic Design. 347--355.Google Scholar
- MIT. Material property database, thermal silicon oxide. http://www.mit.edu/6.777/matprops/sio2.htm.Google Scholar
- Muttreja, A., Agarwal, N., and Jha, N. K. 2007. CMOS logic design with independent-gate FinFETs. In Proceedings of the International Conference on Computer Design. 560--567.Google Scholar
- Rostami, M. and Mohanram, K. 2011. Dual-Vth independent-gate FinFETs for low power logic circuits. IEEE Trans. Computer-Aided Design 30, 3, 337--349. Google ScholarDigital Library
- Nourani, M., Tehranipoor, M., and Ahmed, N. 2008. Low-transition test pattern generation for BIST-based applications. IEEE Trans. Comput. 57, 3, 303--315. Google ScholarDigital Library
- Nowak, E. J., Aller, I., Ludwig, T., Kim, K., Joshi, R. V., Chuang, C.-T., Bernstein, K., and Puri, R. 2004. Turning silicon on its edge {double gate CMOS/FinFET technology}. IEEE Circuits Devices Mag. 20, 1, 20--31.Google ScholarCross Ref
- Ouyang, J. and Xie, Y. 2008. Power optimization for FinFET-based circuits using genetic algorithms. In Proceedings of the International SOC Conference. 211--214.Google Scholar
- Pacha, C., Von Arnim, K., et al. 2007. Efficiency of low-power design techniques in multi-gate FET CMOS circuits. In Proceedings of the European Solid State Circuits Conference. 111--114.Google Scholar
- Pavlidis, V. F. and Friedman, E. G. 2009. Three-Dimensional Integrated Circuit Design. Morgan Kaufmann. Google ScholarDigital Library
- Poljak, M., Jovanovic, V., and Suligoj, T. 2008. SOI vs. bulk FinFET: Body doping and corner effects influence on device characteristics. In Proceedings of the Mediterranean Electrotechnical Conference. 425--430.Google Scholar
- Rosinger, P., Al-Hashimi, B., and Chakrabarty, K. 2005. Rapid generation of thermal-safe test schedules. In Proceedings of the Design, Automation and Test in Europe Conference. Vol. 2, 840--845. Google ScholarDigital Library
- Sechen, C. and Sangiovanni-Vincentelli, A. L. 1985. The TimberWolf placement and routing package. IEEE J. Solid-State Circ. 20, 2, 510--522.Google ScholarCross Ref
- Shang, L., Peh, L.-S., Kumar, A., and Jha, N. K. 2004. Thermal modeling, characterization and management of on-chip networks. In Proceedings of the International Symposium on Microarchitecture. 67--78. Google ScholarDigital Library
- Simsir, M. O. and Jha, N. K. 2009. Thermal characterization of BIST, scan design and sequential test methodologies. In Proceedings of the International Test Conference. 1--9.Google Scholar
- Simsir, M. O., Bhoj, A. N., and Jha, N. K. 2010. Fault modeling for FinFET circuits. In Proceedings of the International Symposium on Nanoscale Architectures. 41--46. Google ScholarDigital Library
- Sinanoglu, O., Bayraktaroglu, I., and Orailoglu, A. 2003. Reducing average and peak test power through scan chain modification. J. Electron. Test. 19, 457--467. Google ScholarDigital Library
- Skadron, K., Stan, M. R., Sankaranarayanan, K., Huang, W., Velusamy, S., and Tarjan, D. 2004. Temperature-aware microarchitecture: Modeling and implementation. ACM Trans. Archit. Code Optim. 1, 94--125. Google ScholarDigital Library
- Stan, M. R., Skadron, K., Barcella, M., Huang, W., Sankaranarayanan, K., and Velusamy, S. 2003. HotSpot: A dynamic compact thermal model at the processor-architecture level. Microelectron. J. 34, 12, 1153--1165.Google ScholarCross Ref
- Swahn, B. and Hassoun, S. 2006. Gate sizing: FinFETs vs. 32nm bulk MOSFETs. In Proceedings of the Design Automation Conference. 528--531. Google ScholarDigital Library
- Synopsys Corp. 2004. VCS MIX user guide. http://www.synopsys.com.Google Scholar
- Synopsys Corp. 2010a. DFT Compiler scan user guide. http://www.synopsys.com.Google Scholar
- Synopsys Corp. 2010b. TetraMAX ATPG user guide. http://www.synopsys.com.Google Scholar
- Tawfik, S. A. and Kursun, V. 2008. Low-power and compact sequential circuits with independent-gate FinFETs. IEEE Trans. Electron Devices 55, 1, 60--70.Google ScholarCross Ref
- Wang, S. 2007. A BIST TPG for low power dissipation and high fault coverage. IEEE Trans. VLSI Syst. 15, 7, 777--789. Google ScholarDigital Library
- Xiong, S. and Bokor, J. 2003. Sensitivity of double-gate and FinFET devices to process variations. IEEE Trans. Electron Devices 50, 11, 2255--2261.Google ScholarCross Ref
- Yan, H., Zhou, Q., and Hong, X. 2008. Efficient thermal aware placement approach integrated with 3D DCT placement algorithm. In Proceedings of the International Symposium on Quality Electronic Design. 289--292. Google ScholarDigital Library
- Yang, Y., Gu, Z., Zhu, C., Dick, R. P., and Shang, L. 2007. ISAC: Integrated space-and-time-adaptive chip-package thermal analysis. IEEE Trans. Comput.-Aided Des. 26, 1, 86--99. Google ScholarDigital Library
- Yoshida, T. and Watati, M. 2003. A new approach for low-power scan testing. In Proceedings of the International Test Conference. Vol. 1, 480--487.Google Scholar
Index Terms
- Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits
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