J. Andres Torres
ABSTRACT
With the widespread adoption of design for manufacturing techniques and design and process co-optimization as well as the increase in the complexity of the processes to manufacture integrated circuits there is pressing need in finding quickly to calibrate yet accurate and high performing methods to identify layout topologies which may cause yield loss. While full-based simulations provide the most accurate prediction possible their runtime prohibits an adoption at all levels of the design flow. Alternative traditional rule checking including pattern matching techniques are fast but have a limited application in finding locations that were not part the training set. Several approaches to improve the accuracy of the prediction to reduce the number of miss structures and false detections have been proposed, but none have yielded and acceptable tradeoff between accuracy and runtime. This contest is aimed to provide a suite of layouts which highlight the challenges of this application: Widely different classes, limited amount of data and low prediction rates.
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Index Terms
- ICCAD-2012 CAD contest in fuzzy pattern matching for physical verification and benchmark suite
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