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Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits

Published:29 May 2013Publication History

ABSTRACT

Capacitance-ratio mismatch in a switched-capacitor circuit could significantly degrade circuit performance. In the nanometer era, the parasitic effects and lengths of interconnects both have significant impacts on the capacitance ratio. This paper presents the first routing work for the problem of coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits. The router adopts a two-stage approach of topology generation followed by detailed routing to route unit capacitors such that the coupling-aware wire length ratio can match the desired capacitance ratio. Given a length ratio, in particular, the length-ratio-matching routing problem can be handled by transforming the problem into an easier classical wirelength minimization one. Experimental results show that our algorithm can solve the addressed problem with substantially smaller costs.

References

  1. L. Baldi, B. Franzini, D. Pandini, and R. Zafalon, "Design solutions for the interconnection parasitic effects in deep sub-micron technologies," Elsevier ME, vol. 55 (1--4), pp. 11--18, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. J. Cohn, D. Garrod, R. Rutenbar, and L. Carley, "KOAN/ANAGRAM II: New tools for device-level analog placement and routing," IEEE JSSC, vol. 26, no. 3, pp. 330--342, 1991.Google ScholarGoogle ScholarCross RefCross Ref
  3. D. Garrod, R. Rutenbar, and L. Carley, "Automatic layout of custom analog cells in ANAGRAM," in Proc. ICCAD, pp. 544--547, 1988.Google ScholarGoogle Scholar
  4. P.-H. Lin, H.-C. Yu, T.-H. Tsai, and S.-C. Lin, "A matching-based placement and routing system for analog design," in Proc. VLSI-DAT, pp. 1--4, 2007.Google ScholarGoogle Scholar
  5. C.-W. Lin, S.-Y, Chen, C.-F. Li, Y.-W. Chang, and C.-L. Yang, "Obstacle-avoiding rectilinear Steiner tree construction based on spanning graphs," IEEE TCAD, vol. 27, no. 4, pp. 643--653, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. C.-W. Lin, J.-M. Lin, Y.-C. Chiu, C.-P. Huang, and S.-J. Chang, "Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits," in Proc. DAC, pp. 528--533, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. J. Lou, S. Krishnamoorthy, and H. S. Sheng, "Estimating routing congestion using probabilistic analysis," IEEE TCAD, vol. 21, no. 1, pp. 32--41, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. J. Ousterhout, "Corner Stitching: A data-structuring technique for VLSI layout tools," IEEE TCAD, vol. 3, no. 1, pp. 87--100, 1984. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. M. M. Ozdal and M. D. F. Wong, "Two-layer bus routing for high-speed printed circuit boards," ACM TODAES, vol. 11, no. 1, pp. 213--227, January 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. M. M. Ozdal and M. D. F. Wong, "Algorithmic study of single-layer bus routing for high-speed boards," IEEE TCAD, vol. 25, no. 3, pp. 490--503, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. M. M. Ozdal and M. D. F. Wong, "A length-matching routing algorithm for high-performance printed circuit boards," IEEE TCAD, vol. 25, no. 12, pp. 2784--2794, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. M. M. Ozdal and R.-F. Hentschke, "Exact route matching algorithms for analog and mixed signal integrated circuits," in Proc. ICCAD, pp. 231--238, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. W. Wolf, "Fabrication and Layout," in Modern VLSI Design: A Systems Approach, pp. 27--82, 1994.Google ScholarGoogle Scholar
  14. J. Xiong and L. He, "Probabilistic congestion model considering shielding for crosstalk reduction," in Proc. ASP-DAC, pp. 739--742, 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. T. Yan and M. D. F. Wong, "BSG-Route: A length-matching router for general topology," in Proc. ICCAD, pp. 499--505, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. L. Zhang, U. Kleine, R. Raut, and Y. Jiang, "Aladin: A layout synthesys tool for analog integrated circuits," Springer AICSP, vol. 46, no. 3, pp. 215--230, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library

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      cover image ACM Conferences
      DAC '13: Proceedings of the 50th Annual Design Automation Conference
      May 2013
      1285 pages
      ISBN:9781450320719
      DOI:10.1145/2463209

      Copyright © 2013 ACM

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      Publication History

      • Published: 29 May 2013

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