Qing Xie
Massoud Pedram
ABSTRACT
Soft-edge flip-flop based pipelines can improve the performance and energy efficiency of circuits operating in the super-threshold (supply voltage) regime by allowing opportunistic time borrowing. The application of this technique to near-threshold regime of operation, however, faces a significant challenge due to large circuit parameter variations that result from manufacturing process imperfections and substrate temperature changes. This paper thus addresses the issue of variability-aware design of the energy-delay optimal linear pipelines that are aimed at operating in both the near-threshold and super-threshold regimes. Precisely, this goal is achieved by deriving the optimal delay line configuration in the soft-edge flip-flops in the near-threshold and the super-threshold operations regimes. The key is to ensure that the same transistor sizes result in effective operation of the delay lines (and hence appropriate settings of the transparency window size) in both operation regimes under the process induced variations. Experimental results demonstrate the efficacy of the proposed solution.
- Dreslinski, R. G., et al. 2010. Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits. Proceedings of the IEEE, 98(2).Google Scholar
Cross Ref
- Markovic, D., Wang, C. C., Alarcon, L. P., Liu, T. T., and Rabaey, and J. M. 2010. Ultralow-power design in near-threshold region. Proceedings of the IEEE, 98(2).Google ScholarCross Ref
- Calhoun, B. H., Wang, A., and Chandrakasan, A. 2005. Modeling and sizing for minimum energy operation in subthreshold circuits. In Journal of Solid State Circuits, 40(9).Google Scholar
- Zhai, B., Hanson, S., Blaauw, D., and Sylvester, D. 2005. Analysis and mitigation of variability in subthreshold design. In Proc. of Int'l Symp. on Low Power Electronics and Design. Google ScholarDigital Library
- Seo, S., et al. 2012. Process variation in near-threshold wide SIMD architectures. In Proc. of Design Automation Conf. Google ScholarDigital Library
- Manne, S., Klauser, A., and Grunwald, D. 1998. Pipeline gating: speculation control for energy reduction. In ACM SIGARCH Computer Architecture News. Google ScholarDigital Library
- Jacobson, H., et al. 2005. Stretching the limits of clock-gating efficiency in server-class processors. In Proc. of High-Performance Computer Architecture. Google ScholarDigital Library
- Partovi, H., Burd, R., Salim, U., Weber, F., DiGregorio, L., and Draper, D. 1996. Flow-through latch and edge-triggered flip-flop hybrid elements. In Proc. of Solid-State Circuits Conf.Google Scholar
- Ghasemazar, M. and Pedram, M. 2008. Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing. In Proc. of Int'l Conf. on Computer Aided Design. Google ScholarDigital Library
- Seok, M., Jeon, D., Chakrabarti, C., Blaauw, D., and Sylvester, D. 2011. Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design. In Proc. of Design Automation Conf. Google ScholarDigital Library
- Datta, A., Bhunia, S., Mukhopadhyay, S., Banerjee, N., and Roy, K. 2005. Statistical modeling of pipeline delay and design of pipeline under process variation to enhance yield in sub-100nm technologies. In Proc. of Design and Test in Europe. Google ScholarDigital Library
- Joshi, V., Blaauw, D., and Sylvester, D. 2007. Soft-edge flip-flops for improved timing yield: design and optimization. In Proc. of Int'l Conf. on Computer Aided Design. Google ScholarDigital Library
- Synopsys 32/28 nm Generic Library: https://sso.synopsys.com/idp/Authn/UserPassword.Google Scholar
- Hanson, S., et al. 2007. Performance and variability optimization strategies in a sub-200mV, 3.5 pJ/inst, 11nW subthreshold processor. In Proc. of Int'l Symp. on VLSI Circuits.Google Scholar
- Fisher, S., Dagan, R., Blonder, S., and Fish, A. 2011. An improved model for delay/energy estimation in near-threshold flip-flops. In Proc. of Int'l Symp. on Circuits and Systems.Google Scholar
- Lotze, N., Ortmanns, M., and Manoli, Y. 2008. Variability of flip-flop timing at sub-threshold voltages. In Proc. of Int'l Symp. on Low Power Electronics and Design. Google ScholarDigital Library
- Pu, Y., et al. 2010. Misleading energy and performance claims in sub/near threshold digital systems. In Proc. of Int'l Conf. on Computer Aided Design. Google ScholarDigital Library
Index Terms
- Variability-aware design of energy-delay optimal linear pipelines operating in the near-threshold regime and above
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