Paul Wettin
Abstract
The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern multicore chips. However, with growing levels of integration, the traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional multihop metal/dielectric-based interconnects. Three-dimensional integration, on-chip photonics, RF, and wireless links have been proposed as radical low-power and low-latency alternatives to the conventional planar wire-based designs. Wireless NoCs with Carbon NanoTube (CNT) antennas are shown to outperform traditional wire-based NoCs significantly in achievable data rate and energy dissipation. However, such emerging and transformative technologies will be prone to high levels of failures due to various issues related to manufacturing challenges and integration. On the other hand, several naturally occurring complex networks such as colonies of microbes and the World Wide Web are known to be inherently robust against high rates of failures and harsh environments. This article advocates adoption of such complex network-based architectures to minimize the effect of wireless link failures on the performance of the NoC. Through cycle-accurate simulations it is shown that the wireless NoC architectures inspired by natural complex networks perform better than their conventional wired counterparts even in the presence of high degrees of link failures. We demonstrate the robustness of the proposed wireless NoC architecture by incorporating both uniform and application-specific traffic patterns.
- Albert, R. and Barabasi, A.-L. 2002. Statistical mechanics of complex networks. Rev. Modern Phys. 74, 47--97.Google Scholar
Cross Ref
- Benini, L. and De Micheli, G. 2002. Networks on chips: A new soc paradigm. IEEE Comput. 35, 1, 70--78. Google ScholarDigital Library
- Bogdan, P. and Marculescu, R. 2007. Quantum-like effects in network-on-chip buffers behavior. In Proceedings of the IEEE Design Automation Conference (DAC'97). 266--267. Google ScholarDigital Library
- Buchanan, M. 2003. Nexus: Small Worlds and the Groundbreaking Theory of Networks. W. W. Norton and Company. Google ScholarDigital Library
- Chang, M.-C. C. F., Cong, J. J., Kaplan, A., Naik, M., Reinman, G., Socher, E., and Tam, S.-W. 2008. CMP network-on-chip overlaid with multi-band rf-interconnect. In Proceeding of the IEEE International Symposium on High-Performance Computer Architecture (HPCA'08). 191--202.Google Scholar
- Chi, H.-C. and Tang, C.-T. 1997. A deadlock-free routing scheme for interconnection networks with irregular topology. In Proceedings of the International Conference on Parallel and Distributed Systems (ICPADS'97). 88--95. Google ScholarDigital Library
- Deb, S., Ganguly, A., Chang, K., Pande, P. P., Belzer, B., and Heo, D. 2010. Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects. In Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP'10). 73--80.Google Scholar
- Duato, J., Yalamanchili, S., and Ni, L. M. 2002. Interconnection Networks-An Engineering Approach. Morgan Kaufmann. Google ScholarDigital Library
- Feero, B. and Pande, P. P. 2009. Networks-on-chip in a three-dimensional environment: A performance evaluation. IEEE Trans. Comput. 58, 1, 32--45. Google ScholarDigital Library
- Ganguly, A., Chang, K., Deb, S., Pande, P. P., Belzer, B., and Teuscher, C. 2011. Scalable hybrid wireless network-on-chip architectures for multi-core systems. IEEE Trans. Comput. 60, 10, 1485--1502. Google ScholarDigital Library
- Green, W. M., Rooks, M. J., Sekaric, L., and Vlasov, Y. A. 2007. Ultra-compact, low rf power, 10gb/s silicon mach-zehnder modulator. Optics Express 15, 25, 17106--17113.Google ScholarCross Ref
- Ho, R., Mai, K. W., and Horowitz, M. A. 2001. The future of wires. Proc. IEEE. 89, 4, 490--504.Google ScholarCross Ref
- Huang, Y., Yin, W.-Y., and Liu, Q. H. 2008. Performance prediction of carbon nanotube bundle dipole antennas. IEEE Trans. Nanotechnol. 7, 3, 331--337. Google ScholarDigital Library
- Humphries, M. D. and Gurney, K. 2008. Network ‘small-world-ness’: A quantitative method for determining canonical network equivalence. PLoS ONE 3, 4.Google ScholarCross Ref
- Joshi, A. J., Batten, C., Kwon, Y.-J., Beamer, S., Shamim, I., Asanovic, K., and Stojanovic, V. D. 2009. Silicon-photonic clos networks for global on-chip communication. In Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (NoCS'09). 124--133. Google ScholarDigital Library
- Kempa, K., Rybczynski, J., Huang, Z., Gregorczyk, K., Vidan, A., Kimball, B., Carlson, J., Benham, G., Wang, Y., Herczynski, A., and Ren, Z. 2007. Carbon nanotubes as optical antennae. Adv. Mater. 19, 421--426.Google ScholarCross Ref
- Krishna, T. T., Kumar, A., Chiang, P. Y., Erez, M., Peh, L.-S. 2008. NoC with near-ideal express virtual channels using global-line communication. In Proceedings of the IEEE Symposium on High Performance Interconnects (HOTI'08). 11--20. Google ScholarDigital Library
- Kumar, A., Peh, L-S., Kundu, P., and Jha, N. K. 2008. Toward ideal on-chip communication using express virtual channels. IEEE Micro. 28, 1, 80--90. Google ScholarDigital Library
- Kurian, G., Miller, J. E., Psota, J., Eastep, J., Liu, J., Michel, J., Kimerling, L. C., and Agarwal, A. 2010. Atac: A 1000-core cache-coherent processor with on-chip optical network. In Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT'10). Google ScholarDigital Library
- Lee, S.-B., Tam, S.-W., Pefkianakis, I., Lu, S., Chang, M. F., Guo, C., Reinman, G., Peng, C., Naik, M., Zhang, L., and Cong, J. 2009. A scalable micro wireless interconnect structure for cmps. In Proceedings of the ACM Annual International Conference on Mobile Computing and Networking (MobiCom'09). 20--25. Google ScholarDigital Library
- Ogras, U. Y. and Marculescu, R. 2006. It's a small world after all: NoC performance optimization via long-range link insertion. IEEE Trans. VLSI Syst. 14, 7, 693--706. Google ScholarDigital Library
- Pande, P. P., Grecu, C. S., Jones, M., Ivanov, A., Saleh, R. A. 2005. Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. Comput. 54, 8, 1025--1040. Google ScholarDigital Library
- Park, D., Eachempati, S., Das, R., Mishra, A. K., Yuan, X., Narayanan, V., and Das, C. R. 2008. MIRA: A multi-layered on-chip interconnect router architecture. In Proceedings of the IEEE International Symposium on Computer Architecture (ISCA'08). 251--261. Google ScholarDigital Library
- Pavlidis, V. F. and Friedman, E. G. 2007. 3-D Topologies for networks-on-chip. IEEE Trans. VLSI 15, 10, 1081--1090. Google ScholarDigital Library
- Petermann, T. and De Los Rios, P. 2005. Spatial small-world networks: A wiring cost perspective. http://arxiv.org/pdf/cond-mat/0501420.pdf.Google Scholar
- Shacham, A., Bergman, K., and Carloni, L. P. 2008. Photonic networks-on-chip for future generations of chip multiprocessors. IEEE Trans. Comput. 57, 9, 1246--1260. Google ScholarDigital Library
- Teuscher, C. 2007. Nature-inspired interconnects for self-assembled large-scale network-on-chip designs. Chaos 17, 2, 026106.Google ScholarCross Ref
- Tilera Corporation. 2013. http://www.tilera.com.Google Scholar
- Vangal, S. R., Howard, J., Ruhl, G., Dighe, S., Wilson, H. A., Tschanz, J. W., Finan, D., Iyer, P., Singh, A. P., Jacob, T., Jain, S., Venkataraman, S., Hoskote, Y. V., and Borkar, N. Y. 2007. An 80-tile 1.28tflops network-on-chip in 65nm cmos. In Proceedings of the IEEE International Solid-State Circuits Conference. 98--589.Google Scholar
- Watts, D. J. and Strogatz, S. H. 1998. Collective dynamics of ‘small-world’ networks. Nature 393, 440--442.Google ScholarCross Ref
- Zhao, D. and Wang, Y. 2008. SD-mac: Design and synthesis of a hardware-efficient collision-free qos-aware mac protocol for wireless network-on-chip. IEEE Trans. Comput. 57, 9, 1230--1245. Google ScholarDigital Library
- Zhou, Y., Johnson, J. L., Wu, L., Maley, S. B., Ural, A., and Xie, H. K. 2008. Design and fabrication of microheaters for localized carbon nanotube growth. In Proceedings of the IEEE Conference on Nanotechnology. 452--455.Google Scholar
Index Terms
- Complex network-enabled robust wireless network-on-chip architectures
Recommendations
Performance evaluation and design trade-offs for wireless network-on-chip architectures
Massive levels of integration are making modern multicore chips all pervasive in several domains. High performance, robustness, and energy-efficiency are crucial for the widespread adoption of such platforms. Networks-on-Chip (NoCs) have emerged as ...
Dual-Level DVFS-Enabled Millimeter-Wave Wireless NoC Architectures
Wireless Network-on-Chip (WiNoC) has emerged as an enabling technology to design low power and high bandwidth massive multicore chips. WiNoCs based on small-world network architecture and designed with incorporating millimeter (mm)-wave on-chip wireless ...
Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems
Multicore platforms are emerging trends in the design of System-on-Chips (SoCs). Interconnect fabrics for these multicore SoCs play a crucial role in achieving the target performance. The Network-on-Chip (NoC) paradigm has been proposed as a promising ...
Comments