Garo Bournoutian
Alex Orailoglu
Abstract
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for general-purpose processors. All the while, it is also expected that these mobile processors be power-conscientious as well as of minimal area impact. These devices pose unique usage demands of ultra-portability but also demand an always-on, continuous data access paradigm. As a result, this dichotomy of continuous execution versus long battery life poses a difficult challenge. This article explores a novel approach to mitigating mobile processor power consumption while abating any significant degradation in execution speed. The concept relies on efficiently leveraging both compile-time and runtime application memory behavior to intelligently target adjustments in the cache to significantly reduce overall processor power, taking into account both the dynamic and leakage power footprint of the cache subsystem. The simulation results show a significant reduction in power consumption of approximately 13% to 29%, while only incurring a nominal increase in execution time and area.
- Agarwal, A., Li, H., and Roy, K. 2002. DRG-cache: A data retention gated-ground cache for low power. In Proceedings of the 39th Conference on Design Automation (DAC'02). 473--478. Google Scholar
Digital Library
- Agarwal, A. and Pudar, S. D. 1993. Column-associative caches: A technique for reducing the miss rate of direct-mapped caches. SIGARCH Comput. Architect. News, 21, 2, 179--190. Google ScholarDigital Library
- Albonesi, D. H. 1999. Selective cache ways: On-demand cache resource allocation. In Proceedings of the 32nd International Symposium on Microarchitecture (MICR0'32). 248--259. Google ScholarDigital Library
- Austin, T., Larson, E., and Ernst, D. 2002. SimpleScalar: An infrastructure for computer system modeling. Computer 35, 2, 59--67. Google ScholarDigital Library
- Bournoutian, G. and Orailoglu, A. 2008. Miss reduction in embedded processors through dynamic, power-friendly cache design. In Proceedings of the 45th Conference on Design Automation (DAC'08). 304--309. Google ScholarDigital Library
- Bournoutian, G. and Orailoglu, A. 2010. Dynamic, non-linear cache architecture for power-sensitive mobile processors. In Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS'10). 187--194. Google ScholarDigital Library
- Brooks, D., Tiwari, V., and Martonosi, M. 2000. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th International Symposium on Computer Architecture (ISCA'00). 83--94. Google ScholarDigital Library
- Calder, B., Grunwald, D., and Emer, J. 1996. Predictive sequential associative cache. In Proceedings of the 2nd Symposium on High-Performance Computer Architecture (HPCA'96). 244--253. Google ScholarDigital Library
- Flautner, K., Kim, N. S., Martin, S., Blaauw, D., and Mudge, T. 2002. Drowsy caches: Simple techniques for reducing leakage power. SIGARCH Comput. Architect. News 30, 2, 148--157. Google ScholarDigital Library
- Ghose, K. and Kamble, M. B. 1999. Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'99). 70--75. Google ScholarDigital Library
- Gordon-Ross, A., Vahid, F., and Dutt, N. 2009. Fast configurable-cache tuning with a unified second-level cache. IEEE Trans. Very Large Scale Integ. Syst. 17, 1, 80--91. Google ScholarDigital Library
- Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin, T. M., Mudge, T., and Brown, R. B. 2001. MiBench: A free, commercially representative embedded benchmark suite. In Proceedings of the International Workshop on Workload Characterization (WWC'01). 3--14. Google ScholarDigital Library
- Hasegawa, A., Kawasaki, I., Yamada, K., Yoshioka, S., Kawasaki, S., and Biswas, P. 1995. SH3: High code density, low power. IEEE Micro 15, 6, 11--19. Google ScholarDigital Library
- Inoue, K., Ishihara, T., and Murakami, K. 1999. Way-predicting set-associative cache for high performance and low energy consumption. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'99). 273--275. Google ScholarDigital Library
- ITRS. 2009. Semiconductor Industry Association. International Technology Roadmap for Semiconductors, 2009. http://www.itrs.net/.Google Scholar
- Jouppi, N. P. 1990. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. SIGARCH Comput. Architect. News, 18, 2SI, 364--373. Google ScholarDigital Library
- Kin, J., Gupta, M., and Mangione-Smith, W. H. 1997. The filter cache: An energy efficient memory structure, In Proceedings of the 30th Intenational Symposium on Microarchitecture (MICRO'30). 184--193. Google ScholarDigital Library
- Ko, U., Balsara, P. T., and Nanda, A. K. 1995. Energy optimization of multi-level processor cache architectures. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'95). 45--49. Google ScholarDigital Library
- Lee, C., Potkonjak, M., and Mangione-Smith, W. H. 1997. MediaBench: A tool for evaluating and synthesizing multimedia and communicatons systems. In Proceedings of the 30th International symposium on Microarchitecture (MICRO30). 330--335. Google ScholarDigital Library
- Lee, L., Kannan, S., and Fridman, J. 2004. MPEG4 video codec on a wireless handset baseband system. In Proceedings of the Workshop Media and Signal Processors for Embedded Systems and SoCs.Google Scholar
- Malik, A., Moyer, B., and Cermak, D. 2000. A low power unified cache architecture providing power and performance flexibility. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'00). 241--243. Google ScholarDigital Library
- Mamidipaka, M. and Dutt, N. 2004. eCACTI: An enhanced power estimation model for on-chip caches. University of California, Irvine Center for Embedded Computer Systems. Tech. rep. TR-04-28.Google Scholar
- Nethercote, N. and Seward, J. 2007. Valgrind: A framework for heavyweight dynamic binary instrumentation. In Proceedings of the Conference on Programming Language Design and Implementation (PLDI'07). 89--100. Google ScholarDigital Library
- Powell, M., Yang, S.-H., Falsafi, B., Roy, K., and Vijaykumar, T. N. 2000. Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'00). 90--95. Google ScholarDigital Library
- Rodriguez, S. and Jacob, B. 2006. Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm). In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'06). 25--30. Google ScholarDigital Library
- SPEC. 2000. SPEC CPU2000 Benchmarks. http://www.spec.org/cpu/.Google Scholar
- Sundararajan, K. T., Jones, T. M., and Topham, N. 2011. Smart cache: A self adaptive cache architecture for energy efficiency. In Proceedings of the International Conference on Embedded Computer Systems (SAMOS'11). 41--50.Google Scholar
- Wilton, S. J. E. and Jouppi, N. P. 1996. CACTI: An enhanced cache access and cycle time model. IEEE J. Solid-State Circuits 31, 5, 677--688.Google ScholarCross Ref
Index Terms
- Application-aware adaptive cache architecture for power-sensitive mobile processors
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