Abstract
Scaling beyond CMOS require a new combination of computing paradigm and new devices. In this context, memristor are often considered as best candidate to implement efficiently synapses in hardware neural networks. In this article, we analyze the impact of memristor parameter variability. We build an analytical model of the global reliability at the crossbar level. It is based on a supervised learning method with multilayer and redundancy extensions. Comparisons with Monte Carlo simulations of small neural network validate our analytical model. It can be used to extrapolate directly the reliability of large-scale neural system. Our extrapolations show that high defect rate and important parameter variability can be handle efficiency with a moderate amount of redundancy.
- Agnus G. et al. 2010. 2-terminal carbon nanotube programmable devices for adaptive architectures. Advanced Material 22, 6, 702--706.Google ScholarCross Ref
- Borghetti, J. et al. 2009. A hybrid nanomemristor/transistor logic circuit capable of self-programming. PNAS, 106, 6, 1699--1703.Google ScholarCross Ref
- Borghetti, J. et al. 2010. Memristive switches enable stateful logic operations via material implication. Nature 464, 873--876.Google ScholarCross Ref
- Chabi, D. et al. 2011. Robust neural logic block (NLB) based on memristor crossbar array. In Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). 137--143. Google ScholarDigital Library
- Chabi D., and Klein J. O. 2010. Hight fault tolerance in neural crossbar. In Proceedings of the 5th International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS). 23--25.Google Scholar
- Chen, Y. et al. 2003. Nanoscale molecular-switch crossbar circuits. Nanotechnology 14, 4, 462--468.Google ScholarCross Ref
- Choi, Y., Lee, M., and Kim, Y. 2004. A two-level redundancy scheme for enhancing scalability of molecular-based crossbar memories. In Proceedings of the 4th IEEE Conference on Nanotechnology. pp. 505--508.Google Scholar
- Chou, S. Y. et al. 1995. Imprint of sub-25 nm vias and trenches in polymers. Appl. Phys. Lett. 67, 3114--3116.Google ScholarCross Ref
- Chua, L. O. and Kang, S. M. 1976. Memristive devices and systems. Proc. IEEE 64, 209--23.Google ScholarCross Ref
- Han, S. 2006. Mixed-signal neuron-synapse implementation for large-scale neural network. Neurocomputing 16, 1860--1867.Google ScholarCross Ref
- He, M., Klein, J.-O., and Belhaire, E. 2008. Design and electrical simulation of on-chip neural learning based on nanocomponents. Electron. Lett. 44, 9, 575--576.Google ScholarCross Ref
- Heath, J. R. et al. 1998. A defect-tolerant computer architecture: Opportunities in nanotechnology. Science 280, 5370, 1716--1721.Google Scholar
- Huang, Y. et al. 2001. Logic gates and computation from assembled nanowire buiding blocks. Science 294, 1313--1317.Google ScholarCross Ref
- Jo, S. H., Chang, T., Ebong, I., Bhadviya, B. B., Mazumder, P., and Lu, W. 2010. Nanoscale memristor device as synapse in neuromorphic systems. Nano Lett. 10, 4, 1297--1301.Google ScholarCross Ref
- Jo, S. H., Kim, K.-H., and Lu, W. 2009. High-density crossbar arrays based on a si memristive system RID C-8780-2011 RID E-8388-2011. Nano Letters 9, 2, 870--874.Google ScholarCross Ref
- Kerlirzin, P. and Vallet, F. 1993. Robustness in Multilayer Perceptrons. Neural Computat. 5, 3, 473--482. Google ScholarDigital Library
- Kockabas, C. et al. 2005 Guided growth of large-scale, horizontally aligned arrays of single-walled carbon nanotubes and their use in thin-film transistors. Small 1, 1110--1116.Google ScholarCross Ref
- Kuekes, P et al. 2005. Defect-tolerant interconnect to nanoelectronic circuits: Internally redundant demultiplexers based on error-correcting codes. Nanotechnology 16, 869--882.Google ScholarCross Ref
- Lee, J. H. and Likharev, K. K. 2007. Defect-tolerant nanoelectronic pattern classifiers. Int. J. Circuit Theory Appl. 35, 3, 239--264. Google ScholarDigital Library
- Liao S. Y. et al. 2011. Design of neuro-inspired learning circuit using OG-CNTFET modelling and technology, IEEE Trans. CAS I, 58, 2172--2181.Google Scholar
- Liang, J. and Wong, H.-S. 2010. Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies. IEEE Trans. Electron Devices, 57, 2531--2538.Google ScholarCross Ref
- Linn, E., Rosezin, R., Kugeler, C., and Waser, R. 2010. Complementary resistive switches for passive nanocrossbar memories. Nat. Mater. 9, 5, 403--406.Google ScholarCross Ref
- Minsky, L. M. and Papert, A. S. 1988. Perceptrons: An Introduction to Computation Geometry. MIT Press, pp. 292.Google Scholar
- Nikolić, K., Sadek, A., and Forshaw, M. 2002. Fault-tolerance technique for nanocomputer. Nanotechnology 13, 280--346.Google ScholarCross Ref
- Querlioz, D., Dollfus, P., Bichler, O., and Gamrat, C. 2011b. Learning with memristive devices: How should we model their behavior? In Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2011). Google ScholarDigital Library
- Pickett, M. D. Medeiros-Ribeiro, G., and Williams, R. S. 2013. A scalable neuristor built with Mott memristors. Nat. Mater. 12, 2, 114--117.Google ScholarCross Ref
- Seo K. et al. 2011. Analog memory and spike-timing-dependent plasticity characteristics of a nanoscale titanium oxide bilayer resistive switching device. Nanotechnology. 22, 25, 254023.Google ScholarCross Ref
- Snider, G. S. 2007. Self-organized computation with unreliable, memristive nanodevices. Nanotechnology, 18, 36, 365202.Google ScholarCross Ref
- Strukov, D. and Likharev, K. 2005. CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices RID B-2689-2009. Nanotechnology 16, 6, 888--900.Google ScholarCross Ref
- Strukov, D. B., Snider, G. S., Stewart, D. R., and Williams, R. S. 2008. The missing memristor found. Nature, 453, 80--83.Google ScholarCross Ref
- Tahoori, M. B. 2008. Defect tolerance in crossbar array nano-architectures. In Emerging Nanotechnologies: Test, Defect Tolerance, and Reliability. M. Tehranipoor, ed., Springer. 121--151.Google Scholar
- Tank, D. and Hopfield, J. 1986. Simple ‘neural’ optimization networks: An A/D converter, signal decision circuit, and a linear programming circuit. IEEE Trans. Circ. Syst. 33, 5, 533.Google ScholarCross Ref
- Waser, R. 2009. Resistive non-volatile memory devices (Invited Paper). Microelectron. Eng. 86, 7--9, 1925--1928. Google ScholarDigital Library
- Widrow, B. 1960. Adaptive Switching Circuits. In IRE WESCON Convention Record, 96--104.Google ScholarCross Ref
- Yang, J. J., Borghetti, J., Murphy, D., Stewart, D. R., and Williams, R. S. 2009. A family of electronically reconfiguiable nanodevices. Adv Mater 21, 3754--3758.Google ScholarCross Ref
- Yang, J. et al. 2012. Engineering nonlinearity into memristors for passive crossbar applications. Appl. Phys. Lett. 100, 11, 113501-113501-4.Google ScholarCross Ref
- Yu, S., Wu, Y., and Wong, H.-S. P. 2011. Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory. Appl. Phys. Lett. 98, 10, 103514.Google ScholarCross Ref
- Xia, Q. et al. 2009. Memristor-CMOS hybrid integrated circuits for reconfigurable logic. Nano Lett. 9, 3640--5.Google ScholarCross Ref
- Zhao, W. S. et al. 2010. Nanotube devices based crossbar architecture: Toward neuromorphic computing, Nanotechnology 21, 175202.Google ScholarCross Ref
- Zhao, W. S. et al. 2012. Cross-point architecture for spin transfer torque magnetic random access memory, IEEE Trans. Nanotech. 11, 907--917. Google ScholarDigital Library
- Zhong, Z. et al. 2003. Nanowire crossbar arrays as address decoders for integrated nanosystems. Science 302, 1377.Google ScholarCross Ref
Index Terms
- Robust learning approach for neuro-inspired nanoscale crossbar architecture
Recommendations
On-Chip Universal Supervised Learning Methods for Neuro-Inspired Block of Memristive Nanodevices
Special Issues on Neuromorphic Computing and Emerging Many-Core Systems for Exascale ComputingScaling down beyond CMOS transistors requires the combination of new computing paradigms and novel devices. In this context, neuromorphic architecture is developed to achieve robust and ultra-low power computing systems. Memristive nanodevices are often ...
In-situ Stochastic Training of MTJ Crossbar based Neural Networks
ISLPED '18: Proceedings of the International Symposium on Low Power Electronics and DesignOwing to high device density, scalability and non-volatility, Magnetic Tunnel Junction-based crossbars have garnered significant interest for implementing the weights of an artificial neural network. The existence of only two stable states in MTJs ...
An efficient neural network approach for nanoscale FinFET modelling and circuit simulation
The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano-circuit simulation. The FinFET used in this work is designed using careful engineering of source–drain extension, which simultaneously ...
Comments