skip to main content
research-article

Robust learning approach for neuro-inspired nanoscale crossbar architecture

Published:13 January 2014Publication History
Skip Abstract Section

Abstract

Scaling beyond CMOS require a new combination of computing paradigm and new devices. In this context, memristor are often considered as best candidate to implement efficiently synapses in hardware neural networks. In this article, we analyze the impact of memristor parameter variability. We build an analytical model of the global reliability at the crossbar level. It is based on a supervised learning method with multilayer and redundancy extensions. Comparisons with Monte Carlo simulations of small neural network validate our analytical model. It can be used to extrapolate directly the reliability of large-scale neural system. Our extrapolations show that high defect rate and important parameter variability can be handle efficiency with a moderate amount of redundancy.

References

  1. Agnus G. et al. 2010. 2-terminal carbon nanotube programmable devices for adaptive architectures. Advanced Material 22, 6, 702--706.Google ScholarGoogle ScholarCross RefCross Ref
  2. Borghetti, J. et al. 2009. A hybrid nanomemristor/transistor logic circuit capable of self-programming. PNAS, 106, 6, 1699--1703.Google ScholarGoogle ScholarCross RefCross Ref
  3. Borghetti, J. et al. 2010. Memristive switches enable stateful logic operations via material implication. Nature 464, 873--876.Google ScholarGoogle ScholarCross RefCross Ref
  4. Chabi, D. et al. 2011. Robust neural logic block (NLB) based on memristor crossbar array. In Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). 137--143. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Chabi D., and Klein J. O. 2010. Hight fault tolerance in neural crossbar. In Proceedings of the 5th International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS). 23--25.Google ScholarGoogle Scholar
  6. Chen, Y. et al. 2003. Nanoscale molecular-switch crossbar circuits. Nanotechnology 14, 4, 462--468.Google ScholarGoogle ScholarCross RefCross Ref
  7. Choi, Y., Lee, M., and Kim, Y. 2004. A two-level redundancy scheme for enhancing scalability of molecular-based crossbar memories. In Proceedings of the 4th IEEE Conference on Nanotechnology. pp. 505--508.Google ScholarGoogle Scholar
  8. Chou, S. Y. et al. 1995. Imprint of sub-25 nm vias and trenches in polymers. Appl. Phys. Lett. 67, 3114--3116.Google ScholarGoogle ScholarCross RefCross Ref
  9. Chua, L. O. and Kang, S. M. 1976. Memristive devices and systems. Proc. IEEE 64, 209--23.Google ScholarGoogle ScholarCross RefCross Ref
  10. Han, S. 2006. Mixed-signal neuron-synapse implementation for large-scale neural network. Neurocomputing 16, 1860--1867.Google ScholarGoogle ScholarCross RefCross Ref
  11. He, M., Klein, J.-O., and Belhaire, E. 2008. Design and electrical simulation of on-chip neural learning based on nanocomponents. Electron. Lett. 44, 9, 575--576.Google ScholarGoogle ScholarCross RefCross Ref
  12. Heath, J. R. et al. 1998. A defect-tolerant computer architecture: Opportunities in nanotechnology. Science 280, 5370, 1716--1721.Google ScholarGoogle Scholar
  13. Huang, Y. et al. 2001. Logic gates and computation from assembled nanowire buiding blocks. Science 294, 1313--1317.Google ScholarGoogle ScholarCross RefCross Ref
  14. Jo, S. H., Chang, T., Ebong, I., Bhadviya, B. B., Mazumder, P., and Lu, W. 2010. Nanoscale memristor device as synapse in neuromorphic systems. Nano Lett. 10, 4, 1297--1301.Google ScholarGoogle ScholarCross RefCross Ref
  15. Jo, S. H., Kim, K.-H., and Lu, W. 2009. High-density crossbar arrays based on a si memristive system RID C-8780-2011 RID E-8388-2011. Nano Letters 9, 2, 870--874.Google ScholarGoogle ScholarCross RefCross Ref
  16. Kerlirzin, P. and Vallet, F. 1993. Robustness in Multilayer Perceptrons. Neural Computat. 5, 3, 473--482. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Kockabas, C. et al. 2005 Guided growth of large-scale, horizontally aligned arrays of single-walled carbon nanotubes and their use in thin-film transistors. Small 1, 1110--1116.Google ScholarGoogle ScholarCross RefCross Ref
  18. Kuekes, P et al. 2005. Defect-tolerant interconnect to nanoelectronic circuits: Internally redundant demultiplexers based on error-correcting codes. Nanotechnology 16, 869--882.Google ScholarGoogle ScholarCross RefCross Ref
  19. Lee, J. H. and Likharev, K. K. 2007. Defect-tolerant nanoelectronic pattern classifiers. Int. J. Circuit Theory Appl. 35, 3, 239--264. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Liao S. Y. et al. 2011. Design of neuro-inspired learning circuit using OG-CNTFET modelling and technology, IEEE Trans. CAS I, 58, 2172--2181.Google ScholarGoogle Scholar
  21. Liang, J. and Wong, H.-S. 2010. Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies. IEEE Trans. Electron Devices, 57, 2531--2538.Google ScholarGoogle ScholarCross RefCross Ref
  22. Linn, E., Rosezin, R., Kugeler, C., and Waser, R. 2010. Complementary resistive switches for passive nanocrossbar memories. Nat. Mater. 9, 5, 403--406.Google ScholarGoogle ScholarCross RefCross Ref
  23. Minsky, L. M. and Papert, A. S. 1988. Perceptrons: An Introduction to Computation Geometry. MIT Press, pp. 292.Google ScholarGoogle Scholar
  24. Nikolić, K., Sadek, A., and Forshaw, M. 2002. Fault-tolerance technique for nanocomputer. Nanotechnology 13, 280--346.Google ScholarGoogle ScholarCross RefCross Ref
  25. Querlioz, D., Dollfus, P., Bichler, O., and Gamrat, C. 2011b. Learning with memristive devices: How should we model their behavior? In Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2011). Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Pickett, M. D. Medeiros-Ribeiro, G., and Williams, R. S. 2013. A scalable neuristor built with Mott memristors. Nat. Mater. 12, 2, 114--117.Google ScholarGoogle ScholarCross RefCross Ref
  27. Seo K. et al. 2011. Analog memory and spike-timing-dependent plasticity characteristics of a nanoscale titanium oxide bilayer resistive switching device. Nanotechnology. 22, 25, 254023.Google ScholarGoogle ScholarCross RefCross Ref
  28. Snider, G. S. 2007. Self-organized computation with unreliable, memristive nanodevices. Nanotechnology, 18, 36, 365202.Google ScholarGoogle ScholarCross RefCross Ref
  29. Strukov, D. and Likharev, K. 2005. CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices RID B-2689-2009. Nanotechnology 16, 6, 888--900.Google ScholarGoogle ScholarCross RefCross Ref
  30. Strukov, D. B., Snider, G. S., Stewart, D. R., and Williams, R. S. 2008. The missing memristor found. Nature, 453, 80--83.Google ScholarGoogle ScholarCross RefCross Ref
  31. Tahoori, M. B. 2008. Defect tolerance in crossbar array nano-architectures. In Emerging Nanotechnologies: Test, Defect Tolerance, and Reliability. M. Tehranipoor, ed., Springer. 121--151.Google ScholarGoogle Scholar
  32. Tank, D. and Hopfield, J. 1986. Simple ‘neural’ optimization networks: An A/D converter, signal decision circuit, and a linear programming circuit. IEEE Trans. Circ. Syst. 33, 5, 533.Google ScholarGoogle ScholarCross RefCross Ref
  33. Waser, R. 2009. Resistive non-volatile memory devices (Invited Paper). Microelectron. Eng. 86, 7--9, 1925--1928. Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. Widrow, B. 1960. Adaptive Switching Circuits. In IRE WESCON Convention Record, 96--104.Google ScholarGoogle ScholarCross RefCross Ref
  35. Yang, J. J., Borghetti, J., Murphy, D., Stewart, D. R., and Williams, R. S. 2009. A family of electronically reconfiguiable nanodevices. Adv Mater 21, 3754--3758.Google ScholarGoogle ScholarCross RefCross Ref
  36. Yang, J. et al. 2012. Engineering nonlinearity into memristors for passive crossbar applications. Appl. Phys. Lett. 100, 11, 113501-113501-4.Google ScholarGoogle ScholarCross RefCross Ref
  37. Yu, S., Wu, Y., and Wong, H.-S. P. 2011. Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory. Appl. Phys. Lett. 98, 10, 103514.Google ScholarGoogle ScholarCross RefCross Ref
  38. Xia, Q. et al. 2009. Memristor-CMOS hybrid integrated circuits for reconfigurable logic. Nano Lett. 9, 3640--5.Google ScholarGoogle ScholarCross RefCross Ref
  39. Zhao, W. S. et al. 2010. Nanotube devices based crossbar architecture: Toward neuromorphic computing, Nanotechnology 21, 175202.Google ScholarGoogle ScholarCross RefCross Ref
  40. Zhao, W. S. et al. 2012. Cross-point architecture for spin transfer torque magnetic random access memory, IEEE Trans. Nanotech. 11, 907--917. Google ScholarGoogle ScholarDigital LibraryDigital Library
  41. Zhong, Z. et al. 2003. Nanowire crossbar arrays as address decoders for integrated nanosystems. Science 302, 1377.Google ScholarGoogle ScholarCross RefCross Ref

Index Terms

  1. Robust learning approach for neuro-inspired nanoscale crossbar architecture

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in

    Full Access

    • Published in

      cover image ACM Journal on Emerging Technologies in Computing Systems
      ACM Journal on Emerging Technologies in Computing Systems  Volume 10, Issue 1
      Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
      January 2014
      210 pages
      ISSN:1550-4832
      EISSN:1550-4840
      DOI:10.1145/2543749
      Issue’s Table of Contents

      Copyright © 2014 ACM

      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 13 January 2014
      • Accepted: 1 December 2012
      • Revised: 1 August 2012
      • Received: 1 March 2012
      Published in jetc Volume 10, Issue 1

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • research-article
      • Research
      • Refereed

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader