ABSTRACT
Data compression is a promising approach for meeting the increasing memory capacity demands expected in future systems. Unfortunately, existing compression algorithms do not translate well when directly applied to main memory because they require the memory controller to perform non-trivial computation to locate a cache line within a compressed memory page, thereby increasing access latency and degrading system performance. Prior proposals for addressing this performance degradation problem are either costly or energy inefficient.
By leveraging the key insight that all cache lines within a page should be compressed to the same size, this paper proposes a new approach to main memory compression--Linearly Compressed Pages (LCP)--that avoids the performance degradation problem without requiring costly or energy-inefficient hardware. We show that any compression algorithm can be adapted to fit the requirements of LCP, and we specifically adapt two previously-proposed compression algorithms to LCP: Frequent Pattern Compression and Base-Delta-Immediate Compression.
Evaluations using benchmarks from SPEC CPU2006 and five server benchmarks show that our approach can significantly increase the effective memory capacity (by 69% on average). In addition to the capacity gains, we evaluate the benefit of transferring consecutive compressed cache lines between the memory controller and main memory. Our new mechanism considerably reduces the memory bandwidth requirements of most of the evaluated benchmarks (by 24% on average), and improves overall performance (by 6.1%/13.9%/10.7% for single-/two-/four-core workloads on average) compared to a baseline system that does not employ main memory compression. LCP also decreases energy consumed by the main memory subsystem (by 9.5% on average over the best prior mechanism).
- B. Abali et al. Memory Expansion Technology (MXT): Software Support and Performance. IBM J. Res. Dev., 2001. Google ScholarDigital Library
- A. R. Alameldeen and D. A. Wood. Adaptive Cache Compression for High-Performance Processors. In ISCA-31, 2004. Google ScholarDigital Library
- A. R. Alameldeen and D. A. Wood. Frequent Pattern Compression: A Significance-Based Compression Scheme for L2 Caches. Tech. Rep., 2004.Google Scholar
- E. D. Berger. Memory Management for High-Performance Applications. PhD thesis, 2002. Google ScholarDigital Library
- X. Chen et al. C-Pack: A High-Performance Microprocessor Cache Compression Algorithm. IEEE Transactions on VLSI Systems, 2010. Google ScholarDigital Library
- E. Cooper-Balis, P. Rosenfeld, and B. Jacob. Buffer-On-Board Memory Systems. In ISCA, 2012. Google ScholarDigital Library
- R. S. de Castro, A. P. do Lago, and D. Da Silva. Adaptive Compressed Caching: Design and Implementation. In SBAC-PAD, 2003. Google ScholarDigital Library
- F. Douglis. The Compression Cache: Using On-line Compression to Extend Physical Memory. In Winter USENIX Conference, 1993.Google Scholar
- J. Dusser et al. Zero-Content Augmented Caches. In ICS, 2009. Google ScholarDigital Library
- M. Ekman and P. Stenström. A Robust Main-Memory Compression Scheme. In ISCA-32, 2005. Google ScholarDigital Library
- M. Farrens and A. Park. Dynamic Base Register Caching: A Technique for Reducing Address Bus Width. In ISCA, 1991. Google ScholarDigital Library
- E. G. Hallnor and S. K. Reinhardt. A Unified Compressed Memory Hierarchy. In HPCA-11, 2005. Google ScholarDigital Library
- D. Huffman. A Method for the Construction of Minimum-Redundancy Codes. IRE, 1952.Google ScholarCross Ref
- S. Iacobovici et al. Effective Stream-Based and Execution-Based Data Prefetching. In ICS, 2004. Google ScholarDigital Library
- Intel Corporation. Intel 64 and IA-32 Architectures Software Developer's Manual, 2013.Google Scholar
- JEDEC. GDDR3 Specific SGRAM Functions, JESD21-C, 2012.Google Scholar
- U. Kang et al. 8Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology. In ISSCC, 2009.Google Scholar
- S. F. Kaplan. Compressed Caching and Modern Virtual Memory Simulation. PhD thesis, 1999. Google ScholarDigital Library
- C. Lefurgy et al. Energy Management for Commercial Servers. In IEEE Computer, 2003. Google ScholarDigital Library
- C. Li, C. Ding, and K. Shen. Quantifying the Cost of Context Switch. In ExpCS, 2007. Google ScholarDigital Library
- S. Li et al. McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures. In MICRO-42, 2009. Google ScholarDigital Library
- P. S. Magnusson et al. Simics: A Full System Simulation Platform. IEEE Computer, 2002. Google ScholarDigital Library
- Micron. 2Gb: x4, x8, x16, DDR3 SDRAM, 2012.Google Scholar
- H. Patil et al. Pinpointing Representative Portions of Large Intel Itanium Programs with Dynamic Instrumentation. In MICRO-37, 2004. Google ScholarDigital Library
- G. Pekhimenko et al. Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches. In PACT, 2012. Google ScholarDigital Library
- G. Pekhimenko et al. Linearly Compressed Pages: A Main Memory Compression Framework with Low Complexity and Low Latency. In SAFARI Technical Report No. 2012--002, 2012.Google ScholarDigital Library
- V. Sathish, M. J. Schulte, and N. S. Kim. Lossless and Lossy Memory I/O Link Compression for Improving Performance of GPGPU Workloads. In PACT, 2012. Google ScholarDigital Library
- A. Snavely and D. M. Tullsen. Symbiotic Jobscheduling for a Simultaneous Multithreaded Processor. In ASPLOS-9, 2000. Google ScholarDigital Library
- SPEC CPU2006. http://www.spec.org/.Google Scholar
- S. Srinath et al. Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. In HPCA-13, 2007. Google ScholarDigital Library
- S. Thoziyoor, N. Muralimanohar, J. H. Ahn, and N. P. Jouppi. CACTI 5.1. Technical Report HPL-2008-20, HP Laboratories, 2008.Google Scholar
- M. Thuresson et al. Memory-Link Compression Schemes: A Value Locality Perspective. IEEE TC, 2008. Google ScholarDigital Library
- Transaction Processing Performance Council. http://www.tpc.org/.Google Scholar
- R. B. Tremaine et al. Pinnacle: IBM MXT in a Memory Controller Chip. IEEE Micro, 2001. Google ScholarDigital Library
- P. R. Wilson, S. F. Kaplan, and Y. Smaragdakis. The Case for Compressed Caching in Virtual Memory Systems. In USENIX Annual Technical Conference, 1999. Google ScholarDigital Library
- J. Yang, R. Gupta, and C. Zhang. Frequent Value Encoding for Low Power Data Buses. ACM TODAES, 2004. Google ScholarDigital Library
- J. Yang, Y. Zhang, and R. Gupta. Frequent Value Compression in Data Caches. In MICRO-33, 2000. Google ScholarDigital Library
- D. H. Yoon, M. K. Jeong, M. Sullivan, and M. Erez. The Dynamic Granularity Memory System. In ISCA, 2012. Google ScholarDigital Library
- Y. Zhang, J. Yang, and R. Gupta. Frequent Value Locality and Value-Centric Data Cache Design. In ASPLOS-9, 2000. Google ScholarDigital Library
- J. Ziv and A. Lempel. A Universal Algorithm for Sequential Data Compression. IEEE TIT, 1977. Google ScholarDigital Library
Index Terms
- Linearly compressed pages: a low-complexity, low-latency main memory compression framework
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