Wenjia Ruan
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Abstract
Time-based transactional memories typically rely on a shared memory counter to ensure consistency. Unfortunately, such a counter can become a bottleneck. In this article, we identify properties of hardware cycle counters that allow their use in place of a shared memory counter. We then devise algorithms that exploit the x86 cycle counter to enable bottleneck-free transactional memory runtime systems. We also consider the impact of privatization safety and hardware ordering constraints on the correctness, performance, and generality of our algorithms.
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Index Terms
- Boosting timestamp-based transactional memory by exploiting hardware cycle counters
Index terms have been assigned to the content through auto-classification.
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