Tong Xu
Abstract
Power gating is a widely used leakage power saving strategy in modern chip designs. However, power gating introduces unique power integrity issues and trade-offs between switching and rush current (wake-up) supply noises. At the same time, the amount of power saving intrinsically trades off with power integrity. In addition, these trade-offs significantly vary with supply voltage. In this article, we propose systemic decoupling capacitors (decaps) optimization strategies that optimally trade-off between power integrity and leakage saving. Specially, new global decap and reroutable decap design concepts are proposed to relax the tight interaction between power integrity and leakage saving of power gated PDNs with a single supply voltage level. Furthermore, we propose a flexible decap allocation technique to deal with the design trade-offs under multiple supply voltage levels. The proposed strategies are implemented in an automatic design flow for choosing the optimal amount of local decaps, global decaps and reroutable decaps. The conducted experiments demonstrate that leakage saving can be increased significantly compared with the conventional PDN design approach with a single supply voltage level using the proposed techniques without jeopardizing power integrity. For PDN designs operating at two supply voltage levels, the optimal performance is achieved at each voltage level.
- Kanak Agarwal, Kevin Nowka, Harmander Deogun, and Dennis Sylvester. 2006. Power gating with multiple sleep modes. In Proceedings of the 7th International Symposium on Quality Electronic Design. IEEE, 633--637. Google Scholar
Digital Library
- Christian Bienia. 2011. Benchmarking modern multiprocessors. Ph.D. Dissertation. Princeton University. Google ScholarDigital Library
- B. Calhoun and A. Chandrakasan. 2003. Standby voltage scaling for reduced power. In Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 639--642.Google Scholar
- Shi-Hao Chen and Jiing-Yuan Lin. 2009. Implementation and verification practices of DVFS and power gating. In Proceedings of the International Symposium on VLSI Design, Automation and Test (VLSI-DAT'09). IEEE, 19--22.Google Scholar
- Sin-Yu Chen, Rung-Bin Lin, Hui-Hsiang Tung, and Kuen-Wey Lin. 2010. Power gating design for standard-cell-like structured ASICs. In Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, 514--519. Google ScholarDigital Library
- Hadi Esmaeilzadeh, Emily Blem, Renee St Amant, Karthikeyan Sankaralingam, and Doug Burger. 2012. Dark silicon and the end of multicore scaling. IEEE Micro 32, 3, 122--134. Google ScholarDigital Library
- Zhou Feng and Peng Li. 2008. Multigrid on GPU: Tackling power grid analysis on parallel SIMT platforms. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'08). 647--654. Google ScholarDigital Library
- Joshua D. Griffin, Tamara G. Kolda, and Robert Michael Lewis. 2008. Asynchronous parallel generating set search for linearly constrained optimization. SIAM J. Sci. Comput. 30, 4, 1892--1924. Google ScholarDigital Library
- Meeta S. Gupta, Jarod L. Oatley, Russ Joseph, Gu-YeonWei, and David M. Brooks. 2007. Understanding voltage variations in chip multiprocessors using a distributed power-delivery network. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE'07). IEEE, 1--6. Google ScholarDigital Library
- Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor Zyuban, Hans Jacobson, and Pradip Bose. 2004. Microarchitectural techniques for power gating of execution units. In Proceedings of the International Symposium on Low Power Electronics and Design. ACM, 32--37. Google ScholarDigital Library
- Intel. 2008. First the tick, now the tock: Next generation Intel microarchitecture (Nehalem). Intel Whitepaper.http://www.intel.com/technology/architecture-silicon/next-gen/whitepaper.pdf.Google Scholar
- Intel. 2013. Mobile 4th gen Intel core processor family: Datasheet, Vol. 1. Intel Whitepaper. http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-m-h-processor-lines-vol-1-datasheet.html.Google Scholar
- ITRS. 2013. The International Technlogy Roadmap for Semiconductors 2013 Edition. http://public.itrs.net/. (2013).Google Scholar
- Hailin Jiang, Malgorzata Marek-Sadowska, and Sani R. Nassif. 2005. Benefits and costs of power-gating technique. In Proceedings of the IEEE International Conference on VLSI in Computers and Processors. IEEE, 559--566. Google ScholarDigital Library
- Ken-ichi Kawasaki, Tetsuyoshi Shiota, Koichi Nakayama, and Atsuki Inoue. 2008. A sub-ms wake-up time power gating technique with bypass power line for rush current support. In Proceedings of the IEEE Symposium on VLSI Circuits. IEEE, 146--147.Google Scholar
- Suhwan Kim, Stephen V. Kosonocky, and Daniel R. Knebel. 2003. Understanding and minimizing ground bounce during mode transition of power gating structures. In Proceedings of the International Symposium on Low Power Electronics and Design. ACM, 22--25. Google ScholarDigital Library
- Joseph N. Kozhaya, Sani R. Nassif, and Farid N. Najm. 2002. A multigrid-like technique for power grid analysis.IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21, 10, 1148--1160. Google ScholarDigital Library
- Suming Lai, Boyuan Yan, and Peng Li. 2012. Stability assurance and design optimization of large power delivery networks with multiple on-chip voltage regulators. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'12). 247--254. Google ScholarDigital Library
- Jacob Leverich, Matteo Monchiero, Vanish Talwar, Parthasarathy Ranganathan, and Christos Kozyrakis. 2009. Power management of datacenter workloads using per-core power gating. Computer Architecture Lett. 8, 2, 48--51. Google ScholarDigital Library
- Sani R. Nassif. 2008. Power grid analysis benchmarks. In Proceedings of the Asia and South Pacific Design Automation Conference. IEEE, 376--381. Google ScholarDigital Library
- Harmander Singh, Kanak Agarwal, Dennis Sylvester, and Kevin J. Nowka. 2007. Enhanced leakage reduction techniques using intermediate strength power gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15, 11, 1215--1224. Google ScholarDigital Library
- Haihua Su, Sachin S. Sapatnekar, and Sani R. Nassif. 2003. Optimal decoupling capacitor sizing and placement for standard-cell layout designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22, 4, 428--436. Google ScholarDigital Library
- Michael B. Taylor. 2012. Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse. In Proceedings of the 49th Annual Design Automation Conference. ACM, 1131--1136. Google ScholarDigital Library
- Tong Xu and Peng Li. 2012. Design and optimization of power gating for DVFS applications. In Proceedings of the 13th International Symposium on Quality Electronic Design. 391--397.Google ScholarCross Ref
- Tong Xu, Peng Li, and Boyuan Yan. 2011. Decoupling for power gating: Sources of power noise and design strategies. In Proceedings of the 48th ACM/EDAC/IEEE Design Automation Conference. 1002--1007. Google ScholarDigital Library
- Zhiyu Zeng, Zhou Feng, Peng Li, and Vivek Sarin. 2011. Locality-driven parallel static analysis for power delivery networks. ACM Trans. Des. Autom. Electron. Syst. 16, 3, Article 28. Google ScholarDigital Library
- Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, and Shu Yan. 2007. On-chip decoupling capacitance and P/G wire co-optimization for dynamic noise. In Proceedings of the 44th ACM/IEEE Design Automation Conference (DAC'07). IEEE, 162--167. Google ScholarDigital Library
- Shiyou Zhao, Kaushik Roy, and Cheng-Kok Koh. 2002. Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst 21, 1, 81--92. Google ScholarDigital Library
Index Terms
- Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating
Recommendations
Decoupling for power gating: sources of power noise and design strategies
DAC '11: Proceedings of the 48th Design Automation ConferencePower gating is essential for controlling leakage power dissipation of modern chip designs. However, power gating introduces unique power delivery integrity issues and tradeoffs between switching and rush current (wake-up) supply noises. In addition, in ...
Standby and dynamic power minimization using enhanced hybrid power gating structure for deep-submicron CMOS VLSI
Scaling down of CMOS Technology reduces supply voltage which helps evade device botch caused by high electric fields in the conducting channel under the gate and gate oxide. Voltage scaling lessens circuit power consumption but increases delay of logic ...
The challenges of implementing fine-grained power gating
GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSIPower consumption in digital systems, especially in portable devices, is a crucial design factor. Due to downscaling of technology, dynamic switching power is not the only relevant source of power consumption anymore as power dissipation caused by ...
Comments