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Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions

Published:13 June 2015Publication History

ABSTRACT

DRAM cells require periodic refreshing to preserve data. In JEDEC DDRx devices, a refresh operation is performed via an auto-refresh command, which refreshes multiple rows in multiple banks simultaneously. The internal implementation of auto-refresh is completely opaque outside the DRAM --- all the memory controller can do is to instruct the DRAM to refresh itself --- the DRAM handles all else, in particular determining which rows in which banks are to be refreshed. This is in conflict with a large body of research on reducing the refresh overhead, in which the memory controller needs fine-grained control over which regions of the memory are refreshed. For example, prior works exploit the fact that a subset of DRAM rows can be refreshed at a slower rate than other rows due to access rate or retention period variations. However, such row-granularity approaches cannot use the standard auto-refresh command, which refreshes an entire batch of rows at once and does not permit skipping of rows. Consequently, prior schemes are forced to use explicit sequences of activate (ACT) and precharge (PRE) operations to mimic row-level refreshing. The drawback is that, compared to using JEDEC's auto-refresh mechanism, using explicit ACT and PRE commands is inefficient, both in terms of performance and power.

In this paper, we show that even when skipping a high percentage of refresh operations, existing row-granurality refresh techniques are mostly ineffective due to the inherent efficiency disparity between ACT/PRE and the JEDEC auto-refresh mechanism. We propose a modification to the DRAM that extends its existing control-register access protocol to include the DRAM's internal refresh counter. We also introduce a new "dummy refresh" command that skips refresh operations and simply increments the internal counter. We show that these modifications allow a memory controller to reduce as many refreshes as in prior work, while achieving significant energy and performance advantages by using auto-refresh most of the time.

References

  1. J. Liu, B. Jaiyen, R. Veras, and O. Mutlu, "RAIDR: Retention-aware intelligent DRAM refresh," 2012 39th Annual International Symposium on Computer Architecture (ISCA), pp. 1--12, Jun. 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. M. Ghosh and H.-H. S. Lee, "Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs," 40th Annual IEEE/ACM International Symposium on Microarchitecture MICRO 2007, pp. 134--145, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. C. Isen and L. John, "ESKIMO - Energy Savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem," in Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, 2009, pp. 337--346. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. T. Hamamoto, S. Sugiura, and S. Sawada, "On the retention time distribution of dynamic random access memory (DRAM)," IEEE Transactions on Electron Devices, vol. 45, no. 6, pp. 1300--1309, Jun. 1998.Google ScholarGoogle ScholarCross RefCross Ref
  5. K. Kim and J. Lee, "A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs," IEEE Electron Device Letters, vol. 30, no. 8, pp. 846--848, Aug. 2009.Google ScholarGoogle ScholarCross RefCross Ref
  6. T. Ohsawa, K. Kai, and K. Murakami, "Optimizing the DRAM Refresh Count for Merged DRAM/Logic LSIs," in ISLPED, 1998, 1998, pp. 82--87. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. JEDEC, "DDR4 STANDARD," 2012.Google ScholarGoogle Scholar
  8. B. Jacob, S. W. Ng, and D. T. Wang, "Memory Systems: Cache, DRAM, Disk." Morgan Kaufmann, ISBN 978-0123797513, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. J. Mukundan, H. Hunter, K. Kim, and J. Stuecheli, "Understanding and Mitigating Refresh Overheads in High-Density DDR4 DRAM Systems," in ISCA, 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. JEDEC, "Low Power Double Data Rate 3," 2012.Google ScholarGoogle Scholar
  11. J. Liu, B. Jaiyen, Y. Kim, C. Wilkerson, and O. Mutlu, "An experimental study of data retention behavior in modern DRAM devices," Proceedings of the 40th Annual International Symposium on Computer Architecture - ISCA '13, p. 60, 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Micron Technology, "Various Methods of DRAM Refresh," 1999.Google ScholarGoogle Scholar
  13. Y. Kim, V. Seshadri, D. Lee, J. Liu, and O. Mutlu, "A case for exploiting subarray-level parallelism (SALP) in DRAM," in ISCA, 2012, vol. 40, no. 3, p. 368. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Micron Technology, "Calculating Memory System Power for DDR3," 2007.Google ScholarGoogle Scholar
  15. K. K. Chang, D. Lee, Z. Chishti, A. R. Alameldeen, C. Wilkerson, Y. Kim, and O. Mutlu, "Improving DRAM Performance by Parallelizing Refreshes with Accesses," in HPCA, 2014.Google ScholarGoogle Scholar
  16. Micron Technology, "4Gb Mobile LPDDR2 SDRAM," 2011.Google ScholarGoogle Scholar
  17. A. Patel, F. Afram, S. Chen, and K. Ghose, "MARSS: a full system simulator for multicore x86 CPUs," in Proceedings of the 48th Design Automation Conference, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. P. Rosenfeld, E. Cooper-Balis, and B. Jacob, "DRAMSim2: A Cycle Accurate Memory System Simulator," Computer Architecture Letters, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. J. L. Henning, "SPEC CPU2006 benchmark descriptions," SIGARCH Comput. Archit. News. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. NASA, "NAS Parallel Benchmarks (NPB 3.3.1)."Google ScholarGoogle Scholar
  21. G. Hamerly, E. Perelman, J. Lau, and B. Calder, "Simpoint 3.0: Faster and more flexible program phase analysis," Journal Of Instruction Level Parallelism, vol. 7, no. 4, pp. 1--28, 2005.Google ScholarGoogle Scholar
  22. I. Hur and C. Lin, "A comprehensive approach to DRAM power management," 2008 IEEE 14th International Symposium on High Performance Computer Architecture, pp. 305--316, 2008.Google ScholarGoogle Scholar
  23. I. Bhati, Z. Chishti, and B. Jacob, "Coordinated Refresh: Energy Efficient Techniques for DRAM Refresh Scheduling," in ISLPED, 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. S. Liu, K. Pattabiraman, T. Moscibroda, and B. G. Zorn, "Flikker: saving DRAM refresh-power through critical data partitioning," in Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems, 2011, pp. 213--224. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. R. K. Venkatesan, S. Herr, and E. Rotenberg, "Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM," in The Twelfth International Symposium on High Performance Computer Architecture 2006, 2006, pp. 157--167.Google ScholarGoogle ScholarCross RefCross Ref
  26. J. Stuecheli, D. Kaseridis, H. C Hunter, and L. K. John, "Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory," 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 375--384, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. J. Liu, B. Jaiyen, Y. Kim, and C. Wilkerson, "An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms," in ISCA, 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens, "Memory access scheduling," in Proceedings of the 27th annual international symposium on Computer architecture - ISCA '00, 2000, pp. 128--138. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Samira Khan, Donghyuk Lee, Yoongu Kim, Alaa Alameldeen, Chris Wilkerson, and Onur Mutlu, "The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study," in The 2014 ACM international conference on Measurement and modeling of computer systems, SIGMETRICS, 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Zehan Cui, Sally A. McKee, Zhongbin Zha, Yungang Bao, and Mingyu Chen, "DTail: a flexible approach to DRAM refresh management," In Proceedings of the 28th ACM international conference on Supercomputing (ICS '14). ACM, New York, NY, USA, 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library

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        cover image ACM Conferences
        ISCA '15: Proceedings of the 42nd Annual International Symposium on Computer Architecture
        June 2015
        768 pages
        ISBN:9781450334020
        DOI:10.1145/2749469

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        • Published: 13 June 2015

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