Pilin Junsangsri
ABSTRACT
This paper presents a new HSPICE macromodel of a Programmable Metalization Cell (PMC). The electrical characteristics of a PMC are simulated by using a geometric model that considers the vertical and lateral growth/disolution of the metallic filament. The selection of the parameters is based on operational features, so the electrical characterization of the PMC is simple, easy to simulate and intuitive. The I-V and R-V plots of a PMC are generated at a very small error compared with experimental data; the proposed model also shows a small error for the relationship between the switching time and the pulse amplitude. The use of a PMC as resistive element in a crossbar memory is also presented; it is shown that a PMC-based crossbar offers substantial improvements over other resistive technologies.
- S. Yu, H. S. P. Wong "Compact Modeling of Conducting-Bridge Random-Access Memory (CBRAM)" IEEE Trans. Electron Devices, Vol. 58, No. 5, May 2011Google Scholar
- D. A. Dimplu, F. Wang "Behavior Modeling of Programmable Metallization Cell Using Verilog-A" 9th International Conference on Information Technology - New Generations 2012, IEEE Computer Society Google ScholarDigital Library
- U. Russo, D. Kamalanathan, D. Ielmini, A. L. Lacaita, M. N. Kozicki "Study of Multilevel Programming in Programmable Metallization Cell (PMC) Memory" IEEE Trans. Electron Devices, Vol. 56, No. 5, May 2009Google ScholarCross Ref
- S. Y. Lee and K. Kim, "Future 1T1C FRAM technologies for highly reliable, high density FRAM," in IEDM Tech. Dig., 2002, pp. 547--550.Google Scholar
- X. Guo, C. Schindler, S. Menzel, and R. Waser, "Understanding the switching-off mechanism in Ag+ migration based resistively switching model systems," Appl. Phys. Lett., vol. 91, no. 13, p. 133513, Sep. 2007Google ScholarCross Ref
- G. Csaba, P. Lugli "Read-Out Design Rules for Molecular Crossbar Architecture" IEEE Trans. on Nanotechnology, Vol. 8, No. 3, May 2009 pp. 369--374 Google ScholarDigital Library
- S. Lin, Y. B. Kim, F. Lombardi "Read-Out Schemes for a CNTFET-based Crossbar Memory" GLSVLSI 20th, pp. 167--170, May 2010 Google ScholarDigital Library
Index Terms
- HSPICE macromodel of a programmable metallization cell (PMC) and its application to memory design
Recommendations
A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File
GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSIThis paper presents the design of a non-volatile register file using cells made of a SRAM and a Programmable Metallization Cell (PMC). The proposed cell is a symmetric 8T2P (8-transistors, 2PMC) design; it utilizes three control lines to ensure the ...
A Novel Design and Simulation of a Compact and Ultra Fast CNTFET Multi-valued Inverter Using HSPICE
UKSIM '12: Proceedings of the 2012 UKSim 14th International Conference on Modelling and SimulationThis paper presents a novel design of a compact multi-valued inverter circuit using Carbon Nanotube Field effect Transistor (CNTFET). All simulations are done by using HSPICE model of CNTFET. The novelty of this paper is by using only one circuit all ...
HSPICE model and circuit simulation for a single-event effect caused by ions at different incident positions
A 3D model of the negative-channel metal-oxide semiconductor (NMOS) structure in a 65-nm complementary metal-oxide semiconductor (CMOS) inverter was built based on technology computer-aided design (TCAD) three-dimensional (3D) device simulation ...
Comments