ABSTRACT
We have integrated an image processing system built around PADDI-2, a custom 48 node MIMD parallel DSP. The system includes image processing algorithms, a graphical SFG tool, a simulator, routing tools, compilers, hardware configuration and debugging tools, application development libraries, and software implementations for hardware verification. The system board,connected to a SPARCstation via a custom Sbus controller, contains 384 processors in 8 VLSI chips. The software environment supports a multiprocessor system under development (VGI-1). The software tools and libraries are modular, with implementation dependencies isolated in layered encapsulations.
- 1.Yeung, A. K. W.,"P^DDI-2 Architecture and Implementation,'' Ph.D. Thesis, University of California, Berkeley, CA, June, 1995.Google Scholar
- 2.Chen, D. C., "Programmable Arithmetic Devices for High Speed Digital Signal Processing," Electronic ResearchLaboratory, Memorandum No. UCB/ERL M92/49, University of California, Berkeley, CA 94720, May 14, 1992.Google Scholar
- 3.Lee, S. Y. and J. K. Aggarwal, "Parallel 2-I) Convolution on a Mesh Connected Array Processor," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. PAMI-9, no. 4, pp. 590 -594, July, 1987. Google ScholarDigital Library
- 4.Sunwoo, M. H. and J. K. Aggarwal, "Flexibly Coupled Multiprocessors for Image Processing," 1988 Intl. Conf. on Parallel Processing, St. Charles, IL, Aug. 1988.Google Scholar
- 5.Webb, J. A., L. G. Hamey, and I. C. Wu, "An Architecture Independent Programming Language for Low-level Vision," Computer Vision, Graphics, and Image Processing, vol. 37, no. 11, pp. 175 1- 1762, Pittsburgh, PA, Nov., 1989. Google ScholarDigital Library
- 6.Stellakis, H. M. and E. S. Manolakos, "A Tri-Array for the Realtime Computation of HigherOrder Moment Estimates," VLSI Signal Processing V, Edited by K. Yao, R. Jain, W. Przytula, J. Rabaey, IEEE New York, pp. 5 1(~ 5 19, New York, 1992.Google Scholar
- 7.Robert, M., M. Paindavoine, and P. Gorria, "Architectures for Integration of Real Time Image Processing Systems," VLSI Signal Processing V, Edited by K. Yao, R. Jain, W. Przytula, J. Rabaey, IEEE New York, pp. 267 - 276, New York, 1992.Google Scholar
- 8.Intel, "iWARPFomm'91,"iWARP Users Meeting, Crystal City, VA, Sept., 1991.Google Scholar
- 9.Borkar, S. and et al, "Supporting Systolic and Memory Communication in iWARP," Proceedings of the 17th International Symposium on Computer Architecture, pp. 71} 8 1, Seattle, WA, May, 1990. Google ScholarDigital Library
- 10.http://infopad. EECS.Berkeley. EDU/spartan/Google Scholar
Index Terms
- A multiprocessor DSP system using PADDI-2
Comments