Bernard L. Peuto
Leonard J. Shustek
- AGA73.Agarwal, D.P., "Design of an Efficient Instruction Set", Carnegie-Mellon, 12/72, iip3Google Scholar
- ACA75.Agajanian, A.H., "A Bibliography on System Performance Evaluation", Computer, November 1975, pps 63-74.Google Scholar
- ALE72.Alexander, W.G., "How a Progrmnming Language is Used", Computer Systems Research Group, University of Toronto, Report CSBG-10, February 1972.Google Scholar
- ALE75.Alexander, W.G., Wortman, D.B., "Static and Dynamic Character istics of XPL Programs", Computer, November 1975, Vol 8, Ii, pps 41-46.Google Scholar
- AMD.Am~ 470V/6 Machine Reference Manual, Amcahl Corporation, Form No. MrM 1000-i, 2rid F~., 1976, Sunnyvale, Calif.Google Scholar
- ANA.Anagnostopoulos, P.C., Michel, M.J., Sockut, G.H., Stabler, G.M., VanDam, "Computer Architecture and Instruction Set Design", NCC 1973, pps 519-527.Google Scholar
- ARB.Ar~x~ckle, R.A., "Computer Analysis and Throughput Evaluation", Computer s and Automation, January 1966, pps 12-15.Google Scholar
- BEN.Bencher, D., "OS/VS2 Release 1 Functional Description", SHARE XL Proceedings, March 1973, pps 320-324.Google Scholar
- CON.Connors, W.D., Mercer, V.S., Sorlini, T.A., "S/360 Instruction Usage Distribution", IBM Systems Development Division, Report 00.2025, Poughkeepsie, N.Y., May 1970.Google Scholar
- EME.Emery, A.R., Alexander, M.T., "A Performance Evaluation of the Amdahl 470V/6 and the IBM 370/168", CMG IV, October 1975, San Francisco.Google Scholar
- FLY.Flynn, M.J., "Trends and Problems in Computer Organizations", Information Processing 74, North Holland Pub. Co., pps 3-10, 1974.Google Scholar
- FOS71a.Foster, C.C., Gonter, R., "Conditional Interpretation of Operation Codes", IEEE Trams. on Computers, January 1971, pps 108-111.Google Scholar
- FOS71b.Foster, C.C., Gonter, R.H., Riseman, E.M., "Measures o f Opcode Util ization", IEEE Transactions on Computers, May 1971, pps 582-584.Google Scholar
- GIB.Gibson, J.C., "The Gibson Mix", IBM System Development Division, Report TR 00.2043, Poughkeepsie, N.Y., 1970. Research done in 1959.Google Scholar
- HAN.Haney, F.M., "Using a Computer to Design Computer Instruction Sets", Carnegie-Mellon, May 1968 PhD Thesis Google ScholarDigital Library
- HEH.Hehner, E.C.R., "Matching Program and Data Representations to a Computing Environment", Computer Systems Research Group, University of Toronto, Report CSRG-44, NovemDer 1974.Google Scholar
- HUG.Hughes, J.H., "A Functional Instruction Mix and Some Related Topics", International Symposium on Computer Performance Modeling Measurement and Evaluation, Cambridge, Mass., March 1976. Google ScholarDigital Library
- IBM.IBM Systen%/370 Model 168 Theory of Operation / Diagrams Manual, Form No. SY22-6931-6936, Volumes 1-6, IBM Corporation, Poughkeepsie, N.Y., 1974.Google Scholar
- JAY.Jay, R.M., National CSS Inc, Distribution at SHARE, New York, August 1975.Google Scholar
- KAP.Kaplan, K.R, winder, R.O, "Cache-Based Computer Systems", Computer, March 1973, pps 30-36.Google Scholar
- LIP.Lipps, H., "Instruction Timing for the CDC 7600 Computer", European Organization for Nuclear Research, CERN 75-19, Geneva, December 1975.Google Scholar
- LUN.Lunde, A., "Evaluation of Instruction Set Processor Architecture by Program Tracing", Department of Computer Science, Carnegie-Mellon University, Pittsburgh, Pa., July 1974.Google Scholar
- MER.Merrill, B., "370/168 Cache Memory Performance", SHARE Computer Measurement and Evaluation Newsletter, July 1974, pps 98-101.Google Scholar
- MUR.Murphey, J.D., and Wade, R.M., "The IBM 360/195 in a world of Mixed Job Streams", Datamation, April 1970, pps 72-79.Google Scholar
- ROS.Rossmann, G.E., Palyn Associates, unpublished comn~m~ication.Google Scholar
- SNI.Snider, D.R., et al, "Comparison of the Amdahl 470 V/6 and the IBM 370/195 Using Benchmarks", Argonne National Laboratory Report ANL-76-50, March 1976.Google Scholar
- VAN.VanTuyl, W.H., "An Engineering View of Performance, IBM System/370 Model 168", SHARE Computer Measurement and Evaluation Selected Papers, Volmne II, p 816-829, August 1973Google Scholar
- WIN.Winder, R.O., "A Data Base for Computer Performance Evaluation", Computer, March 1973, pps 25-29.Google Scholar
Index Terms
- An instruction timing model of CPU performance
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