Grace Li Zhang
Ulf Schlichtmann
ABSTRACT
At nanometer manufacturing technology nodes, process variations significantly affect circuit performance. To combat them, post-silicon clock tuning buffers can be deployed to balance timing budgets of critical paths for each individual chip after manufacturing. The challenge of this method is that path delays should be measured for each chip to configure the tuning buffers properly. Current methods for this delay measurement rely on path-wise frequency stepping. This strategy, however, requires too much time from expensive testers. In this paper, we propose an efficient delay test framework (EffiTest) to solve the post-silicon testing problem by aligning path delays using the already-existing tuning buffers in the circuit. In addition, we only test representative paths and the delays of other paths are estimated by statistical delay prediction. Experimental results demonstrate that the proposed method can reduce the number of frequency stepping iterations by more than 94% with only a slight yield loss.
- S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E. Alon, and M. Horowitz. The implementation of a 2-core, multi-threaded Itanium family processor. IEEE J. Solid-State Circuits, 41(1):197--209, January 2006.Google Scholar
Cross Ref
- J. Tsai, D. Baik, C. C.-P. Chen, and K. K. Saluja. A yield improvement methodology using pre- and post-silicon statistical clock scheduling. In Proc. Int. Conf. Comput.-Aided Des., pages 611--618, 2004. Google ScholarDigital Library
- J. Tsai, L. Zhang, and C. C.-P. Chen. Statistical timing analysis driven post-silicon-tunable clock-tree synthesis. In Proc. Int. Conf. Comput.-Aided Des., pages 575--581, 2005. Google ScholarDigital Library
- V. Khandelwal and A. Srivastava. Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation. In Proc. Int. Symp. Phys. Des., pages 11--18, 2007. Google ScholarDigital Library
- K. Nagaraj and S. Kundu. A study on placement of post silicon clock tuning buffers for mitigating impact of process variation. In Proc. Design, Autom., and Test Europe Conf., pages 292--295, 2009. Google ScholarDigital Library
- Z. Lak and N. Nicolici. A novel algorithmic approach to aid post-silicon delay measurement and clock tuning. IEEE Trans. Comput., 63(5):1074--1084, May 2014. Google ScholarDigital Library
- B. Li, N. Chen, and U. Schlichtmann. Fast statistical timing analysis for circuits with post-silicon tunable clock buffers. In Proc. Int. Conf. Comput.-Aided Des., pages 111--117, 2011. Google ScholarDigital Library
- K. Nagaraj and S. Kundu. An automatic post silicon clock tuning system for improving system performance based on tester measurements. In Proc. Int. Test Conf., pages 1--8, 2008.Google ScholarCross Ref
- D. Tadesse, J. Grodstein, and R. I. Bahar. AutoRex: An automated post-silicon clock tuning tool. In Proc. Int. Test Conf., pages 1--10, 2009.Google ScholarCross Ref
- D. Blaauw, K. Chopra, A. Srivastava, and L. Scheffer. Statistical timing analysis: from basic principles to state of the art. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 27(4):589--607, April 2008. Google ScholarDigital Library
- J. P. Fishburn. Clock skew optimization. IEEE Trans. Comput., 39(7):945--951, July 1990. Google ScholarDigital Library
- Grace Li Zhang, Bing Li, and Ulf Schlichtmann. Sampling-based buffer insertion for post-silicon yield improvement under process variability. In Proc. Design, Autom., and Test Europe Conf., 2016.Google ScholarCross Ref
- R. A. Johnson and D. W. Wichern. Applied multivariate statistical analysis. Pearson Prentice Hall, Upper Saddle River, 2007.Google Scholar
- Q. Liu and S. S. Sapatnekar. A framework for scalable post-silicon statistical delay prediction under process variations. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 28(8):1201--1212, August 2009. Google ScholarDigital Library
- J. Singh and S. S. Sapatnekar. A scalable statistical static timing analyzer incorporating correlated non-gaussian and gaussian parameter variations. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 27(1):160--173, January 2008. Google ScholarDigital Library
- I. T. Jolliffe. Principal Component Analysis. Springer, 2002.Google Scholar
- H. Chang and S. S. Sapatnekar. Statistical timing analysis under spatial correlations. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 24(9):1467--1482, September 2005. Google ScholarDigital Library
- D. S. Chen, R. G. Batson, and Y. Dang. Applied Integer Programming: Modeling and Solution. Wiley, 2011.Google Scholar
- S. Tam, S. Rusu, U. Nagarji Desai, R. Kim, Ji Zhang, and I. Young. Clock generation and distribution for the first IA-64 microprocessor. IEEE J. Solid-State Circuits, 35(11):1545--1552, November 2000.Google ScholarCross Ref
- Gurobi Optimization, Inc. Gurobi optimizer reference manual, 2013.Google Scholar
- EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers
Recommendations
Analysis of power-performance for ultra-thin-body GeOI logic circuits
ISLPED '11: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and designThis work analyzes the power-performance of the emerging Ultra-Thin-Body (UTB) GeOI devices for logic circuit applications. The impacts of temperature and Vdd scaling on the leakage/delay are studied. Compared with the subthreshold leakage dominated SOI ...
Modeling and mitigating NBTI in nanoscale circuits
IOLTS '11: Proceedings of the 2011 IEEE 17th International On-Line Testing SymposiumAs semiconductor manufacturing has entered into nanoscale era, performance degradation due to Negative Bias Temperature Instability (NBTI) became one of the major threats to circuits reliability. In this paper, we present an NBTI gate delay model and a ...
The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits
Special issue on low power electronics and designThe yield of low voltage digital circuits is found to he sensitive to local gate delay variations due to uncorrelated intra-die parameter deviations. Caused by statistical deviations of the doping concentration they lead to more pronounced delay ...
Comments