Sumitha George
John Sampson
ABSTRACT
Ferroelectric FETs (FEFETs) offer intriguing possibilities for the design of low power nonvolatile memories by virtue of their three-terminal structure coupled with the ability of the ferroelectric (FE) material to retain its polarization in the absence of an electric field. Utilizing the distinct features of FEFETs, we propose a 2-transistor (2T) FEFET-based nonvolatile memory with separate read and write paths. With proper co-design at the device, cell and array levels, the proposed design achieves non-destructive read and lower write power at iso-write speed compared to standard FERAM. In addition, the FEFET-based memory exhibits high distinguishability with six orders of magnitude difference in the read currents corresponding to the two states. Comparative analysis based on experimentally calibrated models shows significant improvement of access energy-delay. For example, at a fixed write time of 550ps, the write voltage and energy are 58.5% and 67.7% lower than FERAM, respectively. These benefits are achieved with 2.4 times the area overhead. Further exploration of the proposed FEFET memory in energy harvesting nonvolatile processors shows an average improvement of 27% in forward progress over FERAM.
- Y. Liu, et al. Ambient energy harvesting nonvolatile processors: from circuit to system. In DAC, ACM, 2015. Google Scholar
Digital Library
- C. W. Smullen, et al. Relaxing non-volatility for fast and energyefficient STT-RAM caches. In HPCA, pages 50--61, 2011. Google ScholarDigital Library
- X. Li, et al. RF-powered systems using steep-slope devices, In NEWCAS, pages 73--76, 2014.Google ScholarCross Ref
- K. Ma, et al. Architecture exploration for ambient energy harvesting nonvolatile processors. In HPCA, pages 526--537, 2015.Google ScholarCross Ref
- A. Chen. Emerging nonvolatile memory (NVM) technologies. In ESSDERC, pages 109--113, 2015.Google ScholarCross Ref
- Y. Wang, et al. A 3us Wake-up Time Nonvolatile Processor Based on Ferroelectric Flip-Flops. In ESSCIRC, 2012.Google ScholarCross Ref
- K. L. Wang, et al. 2013. Low-power nonvolatile spintronic memory: STT-RAM and beyond. Journal of Physics D: Applied Physics, 46(7), 074003.Google ScholarCross Ref
- A. Sheikholeslami and P. G. Gulak. A survey of circuit innovations in ferroelectric random-access memories. Proceedings of the IEEE, 88(5): 667--689, 2000.Google ScholarCross Ref
- S. Das and J. Appenzeller. FETRAM. An organic ferroelectric material based novel random access memory cell. Nano letters 11(9): 4003--4007, 2011.Google Scholar
- T. Hatanaka, et al. Ferroelectric (Fe)-NAND flash memory with batch write algorithm and smart data store to the nonvolatile page buffer for data center application high-speed and highly reliable enterprise solidstate drives. JSSC, 45(10): 2156--2164, 2010.Google Scholar
- A. I. Khan, et al. Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation. In IEDM, pages 11.3.1--11.3.4, 2011.Google ScholarCross Ref
- S. Salahuddin and S. Datta. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano letters, 8(2): 405--410, 2008.Google Scholar
- K. Karda, et al. An anti-ferroelectric gated Landau transistor to achieve sub-60 mV/dec switching at low voltage and high speed. Applied Physics Letters, 106(16), 163501, 2015.Google ScholarCross Ref
- http://ptm.asu.edu/Google Scholar
- Y. Kim, S. H. Choday, et al. DSH-MRAM: Differential spin Hall MRAM for on-chip memories. In IEEE Electron Device Letters, 34(10), pages 1259--1261, 2013.Google Scholar
- C. W. Yeung, et al, Low power negative capacitance FETs for future quantum-well body technology, In VLSI-TSA, pages 1--2, 2013.Google Scholar
- M. Qazi, et al. A low-voltage 1 Mb FRAM in 0.13 m CMOS featuring time-to-digital sensing for expanded operating margin. Solid-State Circuits, IEEE Journal of 47(1), pages 141--150, 2012.Google Scholar
- FRAM Guide book, Fujitsu Semiconductor manual, 2005Google Scholar
- M. F. Chang, et al. Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 5(2), pages 183--193, 2015.Google ScholarCross Ref
- S. S. Sheu and M. F. Chang. A 4Mb embedded SLC Resistive-RAM macro with 7.2ns read-write random access time and 160ns MLCaccess capability. In ISSCC, pages 200--201, Feb 2011Google Scholar
- M. F. Chang, et al. Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme. IEEE JSSC, 49(4), pages 908--916, 2014.Google Scholar
- M. F. Chang, et al. A 0.5V 4Mb Logic-Process Compatible Embedded Resistive RAM (ReRAM) in 65nm CMOS Using Low Voltage Current-Mode Sensing Scheme with 45ns Random Read Time. In ISSCC), pages 434--435, 2012.Google ScholarCross Ref
- M. F. Chang, et al, An offset tolerant current-sampling-based sense amplifier for sub-100nA-cell-current nonvolatile memory. IEEE ISSCC, pages. 206--207, Feb 2011.Google ScholarCross Ref
- M. R. Guthaus, et al. Mibench: A free, commercially representative embedded benchmark suite. In Workload Characterization, IEEE International Workshop on, pages 3--14, 2001. Google ScholarDigital Library
- Nonvolatile memory design based on ferroelectric FETs
Recommendations
A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETs
DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019Making embedded memory symmetric provides the capability of memory access in both rows and columns, which brings new opportunities of significant energy and time savings if only a portion of data in the words need to be accessed. This work investigates ...
Endurance-Aware Allocation of Data Variables on NVM-Based Scratchpad Memory in Real-Time Embedded Systems
Nonvolatile memory (NVM) has many benefits compared to the traditional static RAM, such as improved reliability and reduced power consumption, but it has long write latency and limited write endurance. Scratchpad memory (SPM) is software-managed small on-...
Ferroelectric Transistor based Non-Volatile Flip-Flop
ISLPED '16: Proceedings of the 2016 International Symposium on Low Power Electronics and DesignWe present a non-volatile flip-flop with a feature to back-up the state in a ferroelectric transistor (FEFET) during power failure or supply gating. The data is stored in the form of polarization of the ferroelectric (FE) layer in the gate stack of the ...
Comments