Hussam Amrouch
ABSTRACT
Due to aging, circuit reliability has become extraordinary challenging. Reliability-aware circuit design flows do virtually not exist and even research is in its infancy. In this paper, we propose to bring aging awareness to EDA tool flows based on so-called degradation-aware cell libraries. These libraries include detailed delay information of gates/cells under the impact that aging has on both threshold voltage (Vth) and carrier mobility (μ) of transistors. This is unlike state of the art which considers Vth only. We show how ignoring μ degradation leads to underestimating guard-bands by 19% on average. Our investigation revealed that the impact of aging is strongly dependent on the operating conditions of gates (i.e. input signal slew and output load capacitance), and not solely on the duty cycle of transistors. Neglecting this fact results in employing insufficient guard-bands and thus not sustaining reliability during lifetime.
We demonstrate that degradation-aware libraries and tool flows are indispensable for not only accurately estimating guardbands, but also efficiently containing them. By considering aging degradations during logic synthesis, significantly more resilient circuits can be obtained. We further quantify the impact of aging on the degradation of image processing circuits. This goes far beyond investigating aging with respect to path delays solely. We show that in a standard design without any guardbanding, aging leads to unacceptable image quality after just one year. By contrast, if the synthesis tool is provided with the degradation-aware cell library, high image quality is sustained for 10 years (even under worst-case aging and without a guard-band). Hence, using our approach, aging can be effectively suppressed.
- "Degradation-Aware Cell Libraries, V1.0," http://ces.itec.kit.edu/dependable-hardware.phpGoogle Scholar
- V. Santen, H. Amrouch, J. Martinez, M. Nafria, J. Henkel, "Designing Guardbands for Instantaneous Aging Effects," in DAC, 2016 (accepted for publication). Google ScholarDigital Library
- J. Keane and C. H. Kim, "Transistor aging," IEEE Spectrum, 2011.Google Scholar
- E. Gunadi, A. A. Sinkar, N. S. Kim, and M. H. Lipasti, "Combating aging with the colt duty cycle equalizer," in MICRO, 2010, pp. 103--114. Google ScholarDigital Library
- "BSIM Compact MOSFET Models for SPICE Simulation," http://www-device.eecs.berkeley.edu/bsim/?page=BSIM4Google Scholar
- K. Joshi, S. Mukhopadhyay, N. Goel, and S. Mahapatra, "A consistent physical framework for N and P BTI in HKMG MOSFETs," in IRPS, 2012, pp. 5A.3.1--5A.3.10.Google Scholar
- J. B. Velamala, V. Ravi, and Y. Cao, "Failure diagnosis of asymmetric aging under NBTI," in ICCAD, 2011, pp. 428--433. Google ScholarDigital Library
- "Nangate, Open Cell Library," http://www.nangate.com/Google Scholar
- D. Lorenz, G. Georgakos, and U. Schlichtmann, "Aging analysis of circuit timing considering NBTI and HCI," in IOLTS, 2009, pp. 3--8.Google Scholar
- W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu et al., "The impact of NBTI on the performance of combinational and sequential circuits," in DAC, 2007, pp. 364--369. Google ScholarDigital Library
- S. Kiamehr, F. Firouzi, and M. B. Tahoori. "Aging-aware timing analysis considering combined effects of NBTI and PBTI," in ISQED, 2013, pp. 53--59Google Scholar
- D. Gnad, M. Shafique, F. Kriebel, S. Rehman, D. Sun, and J. Henkel, "Hayat: Harnessing dark silicon and variability for aging deceleration and balancing," in DAC, 2015. Google ScholarDigital Library
- N. Karimi, A. K. Kanuparthi, X. Wang, O. Sinanoglu, and R. Karri, "MAGIC: Malicious aging in circuits/cores," ACM Trans. Archit. Code Optim., vol. 12, no. 1, 2015. Google ScholarDigital Library
- M. Ebrahimi, F. Oboril, S. Kiamehr, and M. B. Tahoori, "Aging-aware logic synthesis," in ICCAD, 2013, pp. 61--68. Google ScholarDigital Library
- H. Amrouch, V. M. van Santen, T. Ebi, V. Wenzel, and J. Henkel, "Towards interdependencies of aging mechanisms," in ICCAD, 2014, pp. 478--485. Google ScholarDigital Library
- A. Kerber and T. Nigam, "Challenges in the characterization and modeling of BTI induced variability in metal gate / High-k CMOS technologies," in IRPS, 2013.Google Scholar
- W. Zhao and Y. Cao, "New generation of predictive technology model for sub-45 nm early design exploration," Electron Devices, IEEE Transactions on, vol. 53, no. 11, pp. 2816--2823, Nov 2006. http://ptm.asu.edu/Google ScholarCross Ref
- http://iwls.org/iwls2005/benchmarks.htmlGoogle Scholar
- J. Henkel, L. Bauer, J. Becker, O. Bringmann, U. Brinkschulte, S. Chakraborty et al., "Design and architectures for dependable embedded systems," in CODES+ISSS, 2011, pp. 69--78. Google ScholarDigital Library
- http://trace.eas.asu.edu/yuv/index.htmlGoogle Scholar
Index Terms
- Reliability-aware design to suppress aging
Recommendations
Impact of adaptive voltage scaling on aging-aware signoff
DATE '13: Proceedings of the Conference on Design, Automation and Test in EuropeTransistor aging due to bias temperature instability (BTI) is a major reliability concern in sub-32nm technology. Aging decreases performance of digital circuits over the entire IC lifetime. To compensate for aging, designs now typically apply adaptive ...
Towards reliability-aware circuit design in nanoscale finFET technology: new-generation aging model and circuit reliability simulator
ICCAD '17: Proceedings of the 36th International Conference on Computer-Aided DesignIn this paper, an industry-level new-generation EDA solution for reliability-aware design in nanoscale FinFET technology is presented for the first time, with new compact transistor aging models and upgraded circuit reliability simulator. Our work ...
Aging-aware standard cell library design
DATE '14: Proceedings of the conference on Design, Automation & Test in EuropeTransistor aging, mostly due to Bias Temperature Instability (BTI), is one of the major unreliability sources at nanoscale technology nodes. BTI causes the circuit delay to increase and eventually leads to a decrease in the circuit lifetime. Typically, ...
Reviews
Xinfei Guo
In the biological world, humans age over time. Similar to this, small components like transistors in an electronic chip also age as the system runs. This will slow the system down and cause potential failures while the system is still running. Eventually this will lead to the end of the component's life. For a modern processor, there are billions of such components; the failure of one component will have a high possibility of causing the whole system to fail. Due to high performance and power efficiency demands, technology scaling continues. One of the biggest challenges for downscaling is this aging issue. Therefore, dealing with such aging issues is very important to guarantee robustness for a resilient system. Among the different aging mechanisms, bias temperature instability (BTI), which happens in single transistors, has been accepted as the most pronounced one; it slows down the circuit and causes timing violations. Although it is a physical-level issue, the effect can be introduced to upper levels, like the system and application levels. Since BTI is gaining more interest recently, bringing it into the design flow and tools is necessary. In this paper, Amrouch et al. propose a set of BTI-aware cell libraries that can be used directly in electronic design automation tools for synthesizing and timing analysis. Different from other previous work, this paper considers both threshold voltage (Vth) and mobility affected by BTI. The paper also demonstrates that the impact of BTI is highly dependent on the operating conditions of the circuit (for example, signal slew and output capacitance); these factors have been ignored in the previous literature, which can lead to overdesign. This paper also quantifies the impact of BTI at the system level by plugging the cell libraries into an image processing application. Overall, the paper shows the importance and necessity of considering BTI during the design phase, and the proposed library will serve perfectly for this purpose. The proposed BTI-aware cell library will be very useful for the reliability research community since, until now, there have been few circuit-level simulation solutions for capturing the transient behavior of BTI. The introduction of such a library will provide circuit designers with the ability to easily design robust circuits in an early phase by considering all of the metrics, including power, performance, area, and reliability. Online Computing Reviews Service
Access critical reviews of Computing literature here
Become a reviewer for Computing Reviews.
Comments