Ajay Singhvi
Ney L. V. Calazans
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Abstract
Contemporary digitally controlled delay elements (DEs) trade off power overheads and delay quantization error (DQE). This article proposes a new programmable DE that provides a balanced design that yields low power with moderate DQE even under process, voltage, and temperature variations. The element employs and leverages the advantages offered by a 28nm fully depleted silicon on insulator technology, using back body biasing to add an extra dimension to its programmability. To do so, a novel generic delay shift block is proposed, which enables incorporating both fine and coarse delays in a single DE that can be easily integrated into digital systems, which is an advantage over hybrid DEs that rely on analog design.
- B. Arkin. 2004. Realizing a production ATE custom processor and timing IC containing 400 independent low-power and high-linearity timing verniers. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC’04). 348--349. Google Scholar
Cross Ref
- P. A. Beerel, R. O. Ozdag, and M. Ferretti. 2010. A Designer’s Guide to Asynchronous VLSI. Cambridge University Press. Google ScholarDigital Library
- Cadence. 2016. Virtuoso Analog Design Environment Family. Available at https://www.cadence.com.Google Scholar
- B. H. Calhoun and A. P. Chandrakasan. 2005. Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90nm CMOS. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC'05). Vol. 1. 300--599. Google ScholarCross Ref
- A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, L. Benini, A. Macii, E. Macii, and M. Poncino. 2008. Dynamic thermal clock skew compensation using tunable delay buffers. IEEE Transactions on VLSI Systems 16, 6, 639--649. Google ScholarDigital Library
- Y. Choi, N. Chang, and T. Kim. 2007. DC-DC converter-aware power management for low-power embedded systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, 8, 1367--1381. Google ScholarDigital Library
- R. Diamant, R. Ginosar, and C. Sotiriou. 2015. Asynchronous sub-threshold ultra-low power processor. In Proceedings of the International Workshop on Power and Timing Modeling, Optimization, and Simulation (PATMOS’15). 89--96. Google ScholarCross Ref
- J. F. Dickson. 1976. On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique. IEEE Journal of Solid-State Circuits 11, 3, 374--378. Google ScholarCross Ref
- T. Dogsa, M. Solar, and B. Jarc. 2014. Precision delay circuit for analog quadrature signals in Sin/Cos encoders. IEEE Transactions on Instrumentation and Measurement 63, 12, 2795--2803. Google ScholarCross Ref
- P. Flatresse, B. Giraud, J. Noel, B. Pelloux-Prayer, F. Giner, D. Arora, F. Arnaud, et al. 2013. Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC’13). 424--425. Google ScholarCross Ref
- P. Gupta, A. B. Kahng, P. Sharma, and D. Sylvester. 2006. Gate-length biasing for runtime-leakage control. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, 8, 1475--1485. Google ScholarDigital Library
- J. Hamon and E. Beigné. 2013. Automatic leakage control for wide range performance QDI asynchronous circuits in FD-SOI technology. In Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’13). 142--149. Google ScholarDigital Library
- D. Hand, H. Huang, B. Cheng, Y. Zhang, M. T. Moreira, M. Breuer, N. L. V. Calazans, and P. A. Beerel. 2015. Performance optimization and analysis of blade designs under delay variability. In Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’15). 61--68. Google ScholarCross Ref
- G. Heck, L. S. Heck, A. Singhvi, M. T. Moreira, P. A. Beerel, and N. L. V. Calazans. 2015. Analysis and optimization of programmable delay elements for 2-phase bundled-data circuits. In Proceedings of the International Conference on VLSI Design (VLSID’15). 321--326. Google ScholarCross Ref
- T. B. Hook. 2012. Fully depleted devices for designers: FDSOI and FinFETs. In Proceedings of the IEEE Custom Integrated Circuits Conference (CICC’12). 7. Google ScholarCross Ref
- Y. J. Jung, S. W. Lee, D. Shim, W. Kim, C. Kim, and S. I. Cho. 2001. A dual-loop delay-locked loop using multiple voltage-controlled delay lines. IEEE Journal of Solid State Circuits 36, 5, 784--791. Google ScholarCross Ref
- M. D. Ker, S. L. Chen, and C. S. Tsai. 2006. Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes. IEEE Journal of Solid-State Circuits 41, 5, 1100--1107. Google ScholarCross Ref
- G. Kim, M. K. Kim, B. S. Chang, and W. Kim. 1996. A low-voltage, low-power CMOS delay element. IEEE Journal of Solid-State Circuits 31, 7, 966--971. Google ScholarCross Ref
- J. Kwong, Y. K. Ramadass, N. Verma, and A. P. Chandrakasan. 2009. A 65 nm sub-Vt microcontroller with integrated SRAM and switched capacitor DC-DC converter. IEEE Journal of Solid-State Circuits 44, 1, 115--126. Google ScholarCross Ref
- F. S. Lai and C. F. Lee. 2007. On-chip voltage down converter to improve SRAM read/write margin and static power for sub-nano CMOS technology. IEEE Journal of Solid-State Circuits 42, 9, 2061--2070. Google ScholarCross Ref
- C. Lazzari, A. Ziesemer, and R. A. L. Reis. 2009. An automated design methodology for layout generation targeting power leakage minimization. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (ICECS’09). 81--84. Google ScholarCross Ref
- C. F. Lee, W. Lin, F. S. Lai, and S. C. Lin. 2007. On-chip VDC circuit for SRAM power management. In Proceedings of the International Symposium on VLSI Design, Automation, and Test (VLSI-DAT’07). 4. Google ScholarCross Ref
- G. H. Li and H. P. Chou. 2007. A high resolution time-to-digital converter using two-level vernier delay line technique. In Proceedings of the IEEE Nuclear Science Symposium Conference Record (NSS’07). 276--280. Google ScholarCross Ref
- C. H. Lin, W. Haensch, P. Oldiges, H. Wang, R. Williams, J. Chang, M. Guillorn, et al. 2011. Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond. In Proceedings of the Symposium on VLSI Technology (VLSIT’11). 16--17.Google Scholar
- H. Lin and N. H. C. Chen. 2001. New four-phase generation circuits for low-voltage charge pumps. In Proceedings of the EEE International Symposium on Circuits and Systems (ISCAS’01). 504--507.Google Scholar
- N. R. Mahapatra, S. V. Garimella, and A. Tareen. 2000. An empirical and analytical comparison of delay elements and a new delay element design. In Proceedings of the IEEE Computer Society Workshop on VLSI (VLSI’00). 81--86. Google ScholarDigital Library
- N. R. Mahapatra, S. V. Garimella, and A. Tareen. 2002. Comparison and analysis of delay elements. In Proceedings of the Midwest Symposium on Circuits and Systems (MWSCAS’02). 473--476. Google ScholarCross Ref
- M. Maymandi-Nejad and M. Sachdev. 2003. A digitally programmable delay element: Design and analysis. IEEE Transactions on VLSI Systems 11, 5, 871--878. Google ScholarDigital Library
- M. Maymandi-Nejad and M. Sachdev. 2005. A monotonic digitally controlled delay element. IEEE Journal of Solid-State Circuits 40, 11, 2212--2219. Google ScholarCross Ref
- E. McShane and K. Shenai. 2001. A CMOS monolithic 5-MHz, 5-V, 250-mA, 56% efficiency DC/DC switch-mode boost converter with dynamic PWM for embedded power management. In Proceedings of the IEEE Industry Application Society 36th Annual Meeting (IAS’01), Vol. 1. 653--657. Google ScholarCross Ref
- B. M. Moon, Y. J. Park, and D. K. Jeong. 2008. Monotonic wide-range digitally controlled oscillator compensated for supply voltage variation. IEEE Transactions on Circuits and Systems II: Express Briefs 55, 10, 1036--1040. Google ScholarCross Ref
- G. Palumbo and D. Pappalardo. 2010. Charge pump circuits: An overview on design strategies and topologies. IEEE Circuits and Systems Magazine 10, 1, 31--45. Google ScholarDigital Library
- D. Pan, H. W. Li, and B. M. Wilamowski. 2003. A low voltage to high voltage level shifter circuit for MEMS application. In Proceedings of the 15th Biennial University/Government/Industry Microelectronics Symposium (UGIM’03). 128--131. Google ScholarCross Ref
- M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers. 1989. Matching properties of MOS transistors. IEEE Journal of Solid-State Circuits 24, 5, 1433--1439. Google ScholarCross Ref
- B. Pelloux-Prayer, A. Valentian, B. Giraud, Y. Thonnart, J. P. Noel, P. Flatresse, and E. Beigné. 2013. Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology. In Proceedings of the International Conference on Very Large Scale Integration (VLSI-SoC’13). 168--173.Google Scholar
- K. Phang and D. A. Johns. 2001. A 1V 1mW CMOS front-end with on-chip dynamic gate biasing for a 75Mb/s optical receiver. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC’01). 218--219.Google Scholar
- O. Rozeau, M. A. Jaud, T. Poiroux, and M. Benosman. 2012. UTSOI Model 1.1.3. Laboratoire d’électronique et de technologie de l’information (Leti).Google Scholar
- K. Ryu, D. H. Jung, and S. O. Jung. 2013. All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate. In Proceedings of the European Solid-State Circuits Conference (ESSCIRC’13). 41--44. Google ScholarCross Ref
- K. R. A. Sasaki, J. A. Martino, M. Aoulaiche, E. Simoen, and C. Claeys. 2015. Enhanced dynamic threshold UTBB SOI at high temperature. In Proceedings of the Joint International EUROSOI Workshop and the International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS’15). 261--264. Google ScholarCross Ref
- M. Shin, M. Shi, M. Mouis, A. Cros, E. Josse, G. T. Kim, and G. Ghibaudo. 2014. Low temperature characterization of 14nm FDSOI CMOS devices. In Proceedings of the International Workshop on Low Temperature Electronics (WOLTE’14). 29--32. Google ScholarCross Ref
- A. Singhvi, M. T. Moreira, R. Tadros, N. L. V. Calazans, and P. A. Beerel. 2015. A fine-grained, uniform, energy-efficient delay element for FD-SOI technologies. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI’15). Google ScholarCross Ref
- C. Q. Tran, H. Kawaguchi, and T. Sakurai. 2005. Low-power high-speed level shifter design for block-level dynamic voltage scaling environment. In Proceedings of the International Conference on Integrated Circuit Design and Technology (ICICDT'05). 229--232. Google ScholarCross Ref
- Y. Tsividis. 1999. Operation and Modeling of the MOS Transistor. Oxford University Press.Google Scholar
- J. T. Wu and K. L. Chang. 1998. MOS charge pumps for low-voltage operation. IEEE Journal of Solid-State Circuits 33, 4, 592--597. Google ScholarCross Ref
- J. Xiong, V. Zolotov, C. Visweswariah, and P. A. Habitz. 2009. Optimal test margin computation for at-speed structural test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, 9, 1414--1423. Google ScholarDigital Library
- M. Yamaoka, R. Tsuchiya, and T. Kawahara. 2006. SRAM circuit with expanded operating margin and reduced stand-by leakage current using thin-BOX FD-SOI transistors. IEEE Journal of Solid-State Circuits 41, 11, 2366--2372. Google ScholarCross Ref
- W. Yang, C. H. Lin, T. H. Morshed, D. Lu, A. Niknejad, and C. Hu. 2010. BSIMSOIv4.4 MOSFET MODEL Users’ Manual. Regents of the University of California. Available at http://www-device.eecs.berkeley.edu/bsim/Files/BSIMSOI/bsimsoi4p4/BSIMSOIv4.4_UsersManual.pdf.Google Scholar
Index Terms
- A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits
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