- 1.J.Lou, A.Salek, M.Pedram, "An Exact Solution to Simultaneous Technology Mapping and Linear Placement Problem", Proc. Intl. Conf. on CAD, pp.671-675, Nov 1997. Google ScholarDigital Library
- 2.A~Salek, J.Lou, M.Pcdram, ''A Simultaneous Routing Tree and Fanout Optimization Algorithm", Proc. Intl. Conf. on CAD, pp.625- 630, Nov 1998. Google ScholarDigital Library
- 3.O.Coudert, R. Haddad, "New Algorithms for Gate Sizing: a Conggtmtive Study% Proc. 33"d DAC, pp.734-739, Jun 1996. Google ScholarDigital Library
- 4.J.P.Ftshbum, A.E.Du~op, 'TILOS: a Posynomial Programming Approach to Transistor Sizing% Proc. Intl. Conf. on CAD, pp.326- 328, Nov 1985.Google Scholar
- 5.M. Berkelaar, J. Jess, "Gate Sizing in MOS Digital Circuits with Linear Programming% Proc. European DA C, pp.217-221, 1990. Google ScholarDigital Library
- 6.C.P.Chen, C.C.N.Chu, D.F.Wong, "Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation", Proc. Intl. Conf. on CAD, pp.617~624. Nov 1998. Google ScholarDigital Library
- 7."National Technology Roadmap % Semiconductor Industry Association, 1997.Google Scholar
- 8.W. Chuang, LN.Hajj, "Delay and Area Optimization for Compact Placement by Gate Resizing and Relocation", Proc. Intl. Conf. on CAD, pp. 145-148, Nov 1994. Google ScholarDigital Library
- 9.F.R.K.Chung, F.K.Hwang, 'The Largest Minimal Rectilinear Steiner Trees for a Set of N Points Enclosed in a Rectangle with Given Perimeter", "Networks'; 9:19-36, 1979.Google ScholarCross Ref
- 10.D.Luenberger, "Linear and Nonlinear Programming", pp.180, 1984.Google Scholar
- 11.J.M.Kleinhans, G.Sigl, F.M.Johannes, K.J.Antreich, "GORDIAN: VI.~I Placement by Quadratic Progmnmffng and Slicing Optimization'; IEEE Trans. on Computer-Aided Design, vol.10, No.3, pp.356-365, Mar 1991.Google ScholarDigital Library
- 12.B.M. Riess, G.G. Ettelt, "SPEED: Fast and Efficient Timing Driven Placement", Proc. Intl. Symposium Of Circuits and Systems, pp.377- 380, 1995.Google ScholarCross Ref
- 13.M. Berkelaar, "Area-Power-Delay Trade-off in Logic Synthesis~, Ph.D Thesis, Eindhoven University of Technology, 1992.Google Scholar
- 14.P.lLChan, "Algorithms for Library-specific Sizing of Combinational Logic'; Proc. 2~h DAC, pp.353-356, 1990. Google ScholarDigital Library
- 15.C.Beightler, D.T.Philips, "Applied Geometric Programming'; 1976.Google Scholar
- 16.K. O. Kortanek, X. Xu, Y.Ye, "An infeasible interior-point algorithm for solving primal and dual geometric programs~, Mathematical Programming 76, pp.t55-181, 1996. Google ScholarDigital Library
- 17.M.Avriel, R.Dembo, U.Passy, "Solution of Generalized Geometric Programming", International Journal for Numerical Methods in Engineering, vol.9, 1975.Google ScholarCross Ref
- 18.RJ. Duffin, "Linearizing Geometric Programs", SIAM Review, vol. 12, pp.211-237, 1970.Google ScholarDigital Library
Index Terms
- Gate sizing with controlled displacement
Recommendations
Gate sizing: finFETs vs 32nm bulk MOSFETs
DAC '06: Proceedings of the 43rd annual Design Automation ConferenceFinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive current. We investigate in this paper gate sizing of finFET devices, and we ...
Independently-controlled-gate FinFET schmitt trigger sub-threshold SRAMs
In this work, we propose three novel independently-controlled-gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG_ST 8 T SRAM cells utilize split-gate FinFET devices with the front-gate devices serving as the ...
Impact of channel length, gate insulator thickness, gate insulator material, and temperature on the performance of nanoscale FETs
Aggressive technology scaling as per Moore's law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, ...
Comments