Abstract
One challenge for the heterogeneous computing with the FPGA is how to bridge the development gap between SW and HW designs. The high level synthesis (HLS) technique allows producing hardware with high level languages like C. Design tools based on the HLS like Xilinx SDSoC and SDAccel are developed to speedup SW/HW co-designs. However, the developers still require much circuit design skills to use these tools more efficiently. In this paper, we propose a heterogeneous computing platform based on the virtualization technology, namely hCODE.With the help of the virtualization, the HW and SW design can be totally separated. This brings multiple benefits like accelerating a program without modifying or recompiling it, enable high portability and scalability across different HW and operating system.
- D. Evans, "How the Next Evolution of the Internet Is Changing Everything," Cisco Internet Business Solutions Group, Apr. 2011.Google Scholar
- Xilinx, "The Xilinx SDAccel Development Environment - Bringing The Best Performance/Watt to the Data Center," 2014.Google Scholar
- http://opencores.orgGoogle Scholar
- M. Jacobsen, D. Richmond, M. Hogains and R. Kastner, RIFFA 2.1: A reusable integration framework for FPGA accelerators, ACM Transactions on Reconfigurable Technology and Systems, Vol.8, No. 4, Article 22, Sept. 2015. Google ScholarDigital Library
- XILLYBUS Ltd., http://xillybus.comGoogle Scholar
- A. Putnam, et al., A reconfigurable fabric for accelerating large-scale datacenter services, ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), pp.13--24, June 2014. Google ScholarDigital Library
- Xilinx SDAccel, http://www.xilinx.com/products/designtools/software-zone/sdaccel.htmlGoogle Scholar
- Altera SDK for OpenCL, http://dl.altera.com/opencl/Google Scholar
- S. Byma, J. G. Steffan, H. Bannazadeh, A. Leon-Garcia, FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack, IEEE FCCM 2014, pp.109--116, May 2014. Google ScholarDigital Library
- https://cocoapods.orgGoogle Scholar
- R. Mueller, J. Teubner and G. Alonso, Sorting Networks on FPGAs, The International Journal on Very Large Data Bases, Vol. 21, Issue 1, pp 1--23, Feb. 2012. Google ScholarDigital Library
- D. Koch and J. Torresen, FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on FPGAs for large problem sorting, Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays(FPGA), pp. 45--54, Feb. 2011. Google ScholarDigital Library
Recommendations
A Study of FPGA Virtualization and Accelerator Scheduling
ETCD'17: Proceedings of the first Workshop on Emerging Technologies for software-defined and reconfigurable hardware-accelerated Cloud DatacentersDeploying field-programmable gate arrays (FPGAs) on the cloud to accelerate the processing of the explosively growing server workloads is becoming a clear trend today. However, the costs reduction of accelerator design and deployment is still difficult ...
Application Design for Configurable Computing
Configurable computing systems enhance traditional computing systems through the addition of programmable hardware. Configurable computing offers the opportunity to change the partition at run-time by re-programming the hardware. Recent research has ...
Hardware Resource Virtualization for Dynamically Partially Reconfigurable Systems
The dynamic partial reconfiguration technology enables an embedded system to adapt its hardware functionalities at run-time to changing environment conditions. However, reconfigurable hardware functions are still managed as conventional hardware devices,...
Comments