skip to main content
research-article

A Study of Heterogeneous Computing Design Method based on Virtualization Technology

Published:11 January 2017Publication History
Skip Abstract Section

Abstract

One challenge for the heterogeneous computing with the FPGA is how to bridge the development gap between SW and HW designs. The high level synthesis (HLS) technique allows producing hardware with high level languages like C. Design tools based on the HLS like Xilinx SDSoC and SDAccel are developed to speedup SW/HW co-designs. However, the developers still require much circuit design skills to use these tools more efficiently. In this paper, we propose a heterogeneous computing platform based on the virtualization technology, namely hCODE.With the help of the virtualization, the HW and SW design can be totally separated. This brings multiple benefits like accelerating a program without modifying or recompiling it, enable high portability and scalability across different HW and operating system.

References

  1. D. Evans, "How the Next Evolution of the Internet Is Changing Everything," Cisco Internet Business Solutions Group, Apr. 2011.Google ScholarGoogle Scholar
  2. Xilinx, "The Xilinx SDAccel Development Environment - Bringing The Best Performance/Watt to the Data Center," 2014.Google ScholarGoogle Scholar
  3. http://opencores.orgGoogle ScholarGoogle Scholar
  4. M. Jacobsen, D. Richmond, M. Hogains and R. Kastner, RIFFA 2.1: A reusable integration framework for FPGA accelerators, ACM Transactions on Reconfigurable Technology and Systems, Vol.8, No. 4, Article 22, Sept. 2015. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. XILLYBUS Ltd., http://xillybus.comGoogle ScholarGoogle Scholar
  6. A. Putnam, et al., A reconfigurable fabric for accelerating large-scale datacenter services, ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), pp.13--24, June 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Xilinx SDAccel, http://www.xilinx.com/products/designtools/software-zone/sdaccel.htmlGoogle ScholarGoogle Scholar
  8. Altera SDK for OpenCL, http://dl.altera.com/opencl/Google ScholarGoogle Scholar
  9. S. Byma, J. G. Steffan, H. Bannazadeh, A. Leon-Garcia, FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack, IEEE FCCM 2014, pp.109--116, May 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. https://cocoapods.orgGoogle ScholarGoogle Scholar
  11. R. Mueller, J. Teubner and G. Alonso, Sorting Networks on FPGAs, The International Journal on Very Large Data Bases, Vol. 21, Issue 1, pp 1--23, Feb. 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. D. Koch and J. Torresen, FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on FPGAs for large problem sorting, Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays(FPGA), pp. 45--54, Feb. 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library

Recommendations

Comments

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Sign in

Full Access

  • Published in

    cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 44, Issue 4
    HEART '16
    September 2016
    96 pages
    ISSN:0163-5964
    DOI:10.1145/3039902
    Issue’s Table of Contents

    Copyright © 2017 Authors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    • Published: 11 January 2017

    Check for updates

    Qualifiers

    • research-article

PDF Format

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader