Chun-Hao Lai
ABSTRACT
Persistent memory places NVRAM on the memory bus, offering fast access to persistent data. Yet maintaining NVRAM data persistence raises a host of challenges. Most proposed schemes either incur much performance overhead or require substantial modifications to existing architectures.
We propose a persistent memory accelerator design, which guarantees NVRAM data persistence by hardware yet leaving cache hierarchy and memory controller operations unaltered. A nonvolatile transaction cache keeps an alternative version of data updates side-by-side with the cache hierarchy and paves a new persistent path without affecting original processor execution path. As a result, our design achieves the performance close to the one without persistence guarantee.
- F. Bellard. QEMU, a fast and portable dynamic translator. ATEC '05, pages 41--41, Berkeley, CA, USA, 2005. USENIX Association. Google Scholar
Digital Library
- J. Coburn, A. M. Caulfield, A. Akel, L. M. Grupp, R. K. Gupta, R. Jhala, and S. Swanson. NV-heaps: making persistent objects fast and safe with next-generation, non-volatile memories. ASPLOS' 11, pages 105--118. Google ScholarDigital Library
- J. Condit, E. B. Nightingale, C. Frost, E. Ipek, B. Lee, D. Burger, and D. Coetzee. Better I/O through byte-addressable, persistent memory. SOSP '09, pages 133--146, New York, NY, USA, 2009. ACM. Google ScholarDigital Library
- K. Doshi, E. Giles, and P. Varman. Atomic persistence for SCM with a non-intrusive backend controller. HPCA '16, pages 77--89.Google Scholar
- S. R. Dulloor, S. Kumar, A. Keshavamurthy, P. Lantz, D. Reddy, R. Sankaran, and J. Jackson. System software for persistent memory. EuroSys '14, pages 15:1--15:15, 2014. Google ScholarDigital Library
- E. Giles, K. Doshi, and P. Varman. Bridging the programming gap between persistent and volatile memory using wrap. CF '13, pages 30:1--30:10, 2013. Google ScholarDigital Library
- Intel. Revolutionizing the storage media pyramid with 3D XPoint technology. http://www.intel.com/content/www/us/en/architecture-and-technology/non-volatile-memory.html.Google Scholar
- Intel. Intel architecture instruction set extensions programming reference, 2015. https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf.Google Scholar
- A. K. Joseph Izraelevitz, Terence Kelly. Failure-atomic persistent memory updates via justdo logging. ASPLOS '16, pages 427--442, 2016. Google ScholarDigital Library
- A. Joshi, V. Nagarajan, M. Cintra, and S. Viglas. Efficient persist barriers for multicores. MICRO-48, pages 660--671, 2015. Google ScholarDigital Library
- A. Kolli, J. Rosen, S. Diestelhorst, A. Saidi, and S. Pelley. Delegated persist ordering. MICRO-49, pages 1--13, 2016.Google ScholarCross Ref
- Y. Lu, J. Shu, L. Sun, and O. Mutlu. Loose-ordering consistency for persistent memory. In ICCD, 2014.Google ScholarCross Ref
- A. Patel, F. Afram, S. Chen, and K. Ghose. Marss: A full system simulator for multicore x86 cpus. DAC '11, pages 1050--1055, june 2011. Google ScholarDigital Library
- J. Pedicone, T. Chiacchira, and A. Alvarez. Content addressable memory FIFO with and without purging, Apr. 18 2000. US Patent 6,052,757.Google Scholar
- J. Ren, J. Zhao, S. Khan, J. Choi, Y. Wu, and O. Mutlu. ThyNVM: Enabling software-transparent crash consistency in persistent memory systems. MICRO-48, pages 1--13, 2015.Google ScholarDigital Library
- P. Rosenfeld, E. Cooper-Balis, and B. Jacob. DRAMSim2: A cycle accurate memory system simulator. Computer Architecture Letters, 10(1):16--19, 2011. Google ScholarDigital Library
- Z. Sun, X. Bi, H. H. Li, W.-F. Wong, Z.-L. Ong, X. Zhu, and W. Wu. Multi retention level STT-RAM cache designs with a dynamic refresh scheme. MICRO-44, pages 329--338, New York, NY, USA, 2011. ACM. Google ScholarDigital Library
- M. Sunohara, T. Tokunaga, T. Kurihara, and M. Higashi. Silicon interposer with TSVs (through silicon vias) and fine multilayer wiring. In Proc. of the Electronic Components and Technology Conference, pages 847--852, 2008.Google Scholar
- J. Swanson and J. Wickeraad. Apparatus and method for tracking flushes of cache entries in a data processing system, July 8 2003. US Patent 6,591,332.Google Scholar
- H. Volos, A. J. Tack, and M. M. Swift. Mnemosyne: Lightweight persistent memory. ASPLOS XVI, pages 91--104, New York, NY, USA, 2011. ACM. Google ScholarDigital Library
- M. Wu and W. Zwaenepoel. eNVy: A non-volatile, main memory storage system. ASPLOS '94, pages 86--97, 1994. Google ScholarDigital Library
- M. T. Yourst. PTLsim: A cycle accurate full system x86-64 microarchitectural simulator. In ISPASS, pages 23--34. IEEE Computer Society, 2007.Google ScholarCross Ref
- J. Zhao, S. Li, D. H. Yoon, Y. Xie, and N. P. Jouppi. Kiln: Closing the performance gap between systems with and without persistence support. MICRO-46, pages 421--432, 2013. Google ScholarDigital Library
- Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach
Recommendations
Mnemosyne: lightweight persistent memory
ASPLOS '11New storage-class memory (SCM) technologies, such as phase-change memory, STT-RAM, and memristors, promise user-level access to non-volatile storage through regular memory instructions. These memory devices enable fast user-mode access to persistence, ...
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh
Spin-Torque Transfer RAM (STT-RAM) is a promising candidate for SRAM replacement because of its excellent features, such as fast read access, high density, low leakage power, and CMOS technology compatibility. However, wide adoption of STT-RAM as cache ...
Mnemosyne: lightweight persistent memory
ASPLOS '11New storage-class memory (SCM) technologies, such as phase-change memory, STT-RAM, and memristors, promise user-level access to non-volatile storage through regular memory instructions. These memory devices enable fast user-mode access to persistence, ...
Comments