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ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization

Published:01 June 1999Publication History
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References

  1. 1.A. Odabasioglu, M. Celik, L. T. Pileggi, "PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm," 34th DAC, pp. 58-65, 1997 Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. 2.L. Rohrer and L. Pillage, "Asymptotic Waveform Evaluation for Timing Analysis," IEEE Trans. Computer Aided Design, vol. 9, pp. 352-66, 1990.Google ScholarGoogle ScholarCross RefCross Ref
  3. 3.P. Feldmann and R. W. Freund, "Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm," 32nd DAC, pp. 474-79, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. 4.M. Silveira, M. Kamon, I. Elfadel and J. White, "A Coordinate-Transformed Arnoldi Algorithm for Generating Guaranteed Stable Reduced-Order Models of RLC Circuits," 33rd DAC, pp. 288-94, 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. 5.K. Kerns, I. Wemple, A. Yang, "Stable and Efficient Reduction of Substrate Model Networks Using Congruence Transforms," ICCAD 1995, pp. 207-14. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. 6.R. W. Freund and P. Feldmann, "Reduced-Order Modelling of Large Passive Linear Circuits by Means of the SyPVL Algorithm," 33rd DAC, pp. 280-87, 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. 7.K. L. Shepard, V. Narayanan, P. C. Elmendorf, G. Zheng, "Global Harmony: Coupled Noise Analysis for Full-Chip RC Interconnect Networks", 34th DAC, pp. 139-46, 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. 8.B. Sheehan, "Projective Convolution: RLC Model- Order Reduction Using the Impulse Response", DATE 99, 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. 9.C. Ratzlaff and L. Pillage, "RICE: Rapid Interconnect Circuit Evaluation Using AWE," IEEE Trans. CAD, vol. 13, pp. 763-76, 1994.Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. 10.A. George and J. W-H Liu. Computer Solution of Large Sparse Positive Definite Systems. Prentice-Hall, New Jersey, 1981. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. 11.E. A. Guillemin, Synthesis of Passive Networks, John Wiley and Sons, 1957.Google ScholarGoogle Scholar

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  1. ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization

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      cover image ACM Conferences
      DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference
      June 1999
      1000 pages
      ISBN:1581131097
      DOI:10.1145/309847

      Copyright © 1999 ACM

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      Publication History

      • Published: 1 June 1999

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      DAC '99 Paper Acceptance Rate154of451submissions,34%Overall Acceptance Rate1,770of5,499submissions,32%

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