Jian Shen
- 1.T.B. Alexander, K. A. Dickey, D. N. Goldberg, R. V. La Fetra, J. R. McGee, N. Noordeen, and A. Prakash. Verification, characterization, and debugging of the HP PA 7200 processor. In Hewlett-Packard Journal, pages 1- 12, February 1996.Google Scholar
- 2.M. Kantrowitz and L. M. Noack. I'm Done Simulating; Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha microprocessor. In Proc. of the Design Automation Conf., pages 325-333, June 1996. Google ScholarDigital Library
- 3.S. T. Mangelsdorf, R. E Gratias, R. M. Blumberg, and R. Bhatia. Functional verification of the HP PA 8000 processor. In Hewlett-Packard Journal, pages 1-13, August 1997.Google Scholar
- 4.A. Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, M. Molcho, and G. Shurek. Test Program Generation for Functional Verification of PowerPC Processors in IBM. In Proc. of the Design Automation Conf., pages 279-285, June 1995. Google ScholarDigital Library
- 5.J. Shen and J. A. Abraham. Native Mode Functional Test Generation for Microprocessors with Applications to Self Test and Design Validation. In Proc. Intl. Test Conf., pages 990-999, 1998. Google ScholarDigital Library
- 6.C. Hinchcliff. Simplified Microprocessor Test Generation. InProc. Intl. Test Conf., pages 176-180, 1982.Google Scholar
- 7.A.J. van de Goor and O. Jansen. Self Test for the Intel 8085. In Microprocessing and Microprogramming, 29:165-175, 1990. Google ScholarDigital Library
Index Terms
- Functional verification of the equator MAP1000 microprocessor
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