- 1.Chen, Z., Johnson, M., Wei, L., and Roy, K. Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. Proceedings of the Symposium on Low Power Design and Electronics (1998), 239-244. Google ScholarDigital Library
- 2.Cormen, T.H., Leiserson, G.E., and Rivest, R.L. Introduction to Algorithms, The MIT Press, Cambridge, MA, 1990. Google ScholarDigital Library
- 3.Gil, J., Je, M., Lee, J., and Shin, H. A high speed and low power SOI inverter using active body bias. Proceedings of the Symposium on Low Power Electronics and Design.(1998), 59-63. Google ScholarDigital Library
- 4.Halter, J.P., and Najm, F. A gate-level leakage power reduction method for ultra-low-power CMOS circuits. Proceedings of the IEEE Custom Integrated Circuits Conference (1997), 475-478.Google ScholarCross Ref
- 5.Johnson, M.C., Somasekhar, D., and Roy, K. A model for leakage control by MOS transistor stacking. Tech. Rep. TR- ECE 97-12, Purdue University, School of Electrical and Computer Engineering, 1997.Google Scholar
- 6.Kobayashi, T., and Sakurai, T. Self-adjusting thresholdvoltage scheme (SATS) for low-voltage high-speed operation. Proceedings IEEE Custom Integrated Circuits Conference (1994), 271-274.Google ScholarCross Ref
- 7.Kuroda, T., et al. A 0.9v 150MHz 10 mW 4mm2 2-D discrete cosine transform core processor with variablethreshold-voltage scheme. Proceedings IEEE International Solid-State Circuits Conference (1996), 166-167.Google Scholar
- 8.Maxwell, P.C., and Rearick, J.R. A simulation-based method for estimating defect-free IDDQ. Digest of Papers, IEEE International Workshop on IDDQ Testing (1997), 80- 84. Google ScholarDigital Library
- 9.Mutoh, S., et al. 1-v power supply high-speed digital circuit technology with multithreshold-voltage CMOS. IEEE Journal of Solid-State Circuits, vol.30, no.8 (Aug. 1995), 847-853.Google ScholarCross Ref
- 10.Shigematsu, S., et. al. A 1-V high-speed MTCMOS circuit scheme for power-down applications. IEEE Symposium on VLSI Circuits Digest of Technical Papers (1995), 125-126.Google ScholarCross Ref
- 11.Vieri, C., et al. SOIAS: Dynamically variable threshold SOI with active substrate. Proceedings of the Symposium on Low Power Electronics (1995), 86-87.Google ScholarCross Ref
- 12.Wei, L., Chen, Z., Roy, K., Johnson, M.C., Ye, Y., and De, V. Design and optimization of dual threshold circuits for low voltage low power applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.7, no.1 (March 1999), 16-24. Google ScholarDigital Library
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- Leakage control with efficient use of transistor stacks in single threshold CMOS
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Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks
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