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Minimal Disturbed Bits in Writing Resistive Crossbar Memories

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Published:17 July 2018Publication History

ABSTRACT

Resistive memories are promising candidates for non-volatile memories. Write disturb is one of problems that facing this kind of memories. In this paper, the write disturb problem is mathematically formulated in terms of the bias parameters and optimized analytically. A closed form solution for the optimal bias parameters is calculated. Results are compared with the 1/2 and 1/3 bias schemes showing a significant improvement.

References

  1. An Chen. 2015. Analysis of partial bias schemes for the writing of crossbar memory arrays. IEEE Transactions on Electron Devices 62, 9 (2015), 2845--2849.Google ScholarGoogle ScholarCross RefCross Ref
  2. M E Fouda and et al. 2018. Modeling and analysis of passive switching crossbar arrays. IEEE Trans. on Circuits and Systems I: Regular Papers 65, 1 (2018), 270--282.Google ScholarGoogle ScholarCross RefCross Ref
  3. D. Ielmini. 2016. Resistive switching memories based on metal oxides: mechanisms, reliability and scaling. Semiconductor Science and Technology 31, 6 (2016), 063002.Google ScholarGoogle ScholarCross RefCross Ref
  4. H Li and et al. 2014. Write disturb analyses on half-selected cells of cross-point RRAM arrays. In Reliability Physics Symposium, 2014 IEEE Int. IEEE, MY--3.Google ScholarGoogle Scholar
  5. Shimeng Yu and Pai-Yu Chen. 2016. Emerging memory technologies: Recent trends and prospects. IEEE Solid-State Circuits Magazine 8, 2 (2016), 43--56.Google ScholarGoogle ScholarCross RefCross Ref
  6. M A Zidan and et al. 2013. Memristor-based memory: The sneak paths problem and solutions. Microelectronics Journal 44, 2 (2013), 176--183. Google ScholarGoogle ScholarDigital LibraryDigital Library

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  1. Minimal Disturbed Bits in Writing Resistive Crossbar Memories

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    • Published in

      cover image ACM Conferences
      NANOARCH '18: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures
      July 2018
      176 pages
      ISBN:9781450358156
      DOI:10.1145/3232195

      Copyright © 2018 ACM

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 17 July 2018

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      • short-paper
      • Research
      • Refereed limited

      Acceptance Rates

      NANOARCH '18 Paper Acceptance Rate30of56submissions,54%Overall Acceptance Rate55of87submissions,63%

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