Adiseshu Hari
Abstract
Link-striping algorithms are often used to overcome transmission bottlenecks in computer networks. Traditional striping algorithms suffer from two major disadvantages. They provide inadequate load sharing in the presence of variable-length packets, and may result in non-FIFO delivery of data. We describe a new family of link-striping algorithms that solves both problems. Our scheme applies to any layer that can provide multiple FIFO channels. We deal with variable-sized packets by showing how fair-queuing algorithms can be transformed into load-sharing algorithms. Our transformation results in practical load-sharing protocols, and shows a theoretical connection between two seemingly different problems. The same transformation can be applied to obtain load-sharing protocols for links with different capacities. We deal with the FIFO requirement for two separate cases. If a sequence number can be added to each packet, we show how to speed up packet processing by letting the receiver simulate the sender algorithm. If no header can be added, we show how to provide quasi FIFO delivery. Quasi FIFO is FIFO except during occasional periods of loss of synchronization. We argue that quasi FIFO is adequate for most applications. We also describe a simple technique for speedy restoration of synchronization in the event of loss. We develop an architectural framework for transparently embedding our protocol at the network level by striping IP packets across multiple physical interfaces. The resulting stripe protocol has been implemented within the NetBSD kernel. Our measurements and simulations show that the protocol offers scalable throughput even when striping is done over dissimilar links, and that the protocol synchronized quickly after packet loss. Measurements show performance improvements over conventional round-robin striping schemes and striping schemes that do not resequence packets. Some aspects of our solution have been implemented in Cisco's router operating system (IOS 11.3) in the context of Multilink PPP striping.
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Index Terms
- An architecture for packet-striping protocols
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Reviews
Cui-Qing Yang
With the ever-growing power of computer CPUs (such as the recent advent of 1.0 GHz PC processors), network speeds for Internet access and Internet service provider (ISP) backbones usually become the bottlenecks. Although many new technologies, such as DSL, cable modems, Gigabit Ethernet, and WDM fiber, will certainly offer great promise in the future, some of the old gimmicks, such as data striping or reverse multiplexing, which increase communication throughput by “striping” data across multiple network links, can still work their charm. This paper presents a new set of data-striping (packet-striping or channel-striping) algorithms that efficiently handle issues of variable-packet-size and first-in-first-out (FIFO) delivery with packet losses and dynamically varying skews. The most interesting feature of the proposed algorithms is that a theoretical connection (“transformation theorem”) is first established between the well-studied fair-queueing algorithms and the data-striping algorithms of load sharing, and new data striping algorithms surplus round robin (SRR) and generalized round robin (GRR) are then derived as the results of transformation from existing fair-queue ing algorithms. As a demonstration, the implementation, within the NetBSD kernel, of a simple architectural framework for striping IP packets using SRR over multiple data link interfaces (“stripe” protocol) is also included. The performance measurements and simulations show improved results over available striping schemes with scalable throughput, even when striping is done over dissimilar links (ATM and Ethernet), and the protocol synchronizes quickly after packet losses.
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