ABSTRACT
This paper presents the Compaan tool that automatically transforms a nested loop program written in Matlab into a process network specification. The process network model of computation fits better with the new emerging kind of embedded architectures that use coprocessors. Process networks can describe both fine-grained and coarse-grained parallelism, making the mapping of the applications easier.
- 1.A. Abnous and J. Rabaey. Ultra-low-power domain-specific multimedia processors. In VLSI Signal Processing, IX, pages 461-470, 1996.Google Scholar
- 2.P. Clauss and V. Loechner. Parametric analysis of polyhedral iteration spaces. Journal of VLSI Signal Processing, 19:179- 194, July 1998. Google ScholarDigital Library
- 3.E.A. Lee et al. Heterogeneous concurrent modeling and design in java. Technical report, University of California, Dept EECS, Nov. 1998.Google Scholar
- 4.P. Feautrier. Parametric integer programming. Recherche Op~rationelle; Operations Research, 22(3):243-268, 1988.Google ScholarCross Ref
- 5.C. F. Goldfard and P. Prescod. The XML Handbook. Prentice Hall, June 1998. Google ScholarDigital Library
- 6.P. Held. Functional Design of Data-Flow Networks. PhD thesis, Dept. EE, Delft University of Technology, May 1996.Google Scholar
- 7.G. Kahn. The semantics of a simple language for parallel programming. In Proc. of the IFIP Congress 74. North-Holland Publishing Co., 1974.Google Scholar
- 8.B. Kienhuis. Design Space Exploration of Stream-based Datafiow Architectures: Methods and Tools. PhD thesis, Delft University of Technology, Jan. 1999.Google Scholar
- 9.B. Kienhuis. Matparser: An array dataflow analysis compiler. Technical Report UCB/ERL M00/9, University of California, Berkeley, CA-94720, USA, Feb. 2000.Google Scholar
- 10.B. Kienhuis, E. Deprettere, K. Vissers, and P. van der Wolf. The construction of a retargetable simulator for an architecture template. In Proceedings of 6th Int. Workshop on Hardware/Software Codesign, Seattle, Washington, Mar. 15-18 1998. Google ScholarDigital Library
- 11.E. A. Lee and T. M. Parks. Dataflow process networks. Proceedings of the IEEE, 83(5):773-799, May 1995.Google ScholarCross Ref
- 12.J. A. Leijten, J. L. van Meerbergen, A. H. Timmer, and J. A. Jess. Prohid, a data-driven multi-processor architecture for high-performance dsp. In Proc. ED&TC, Mar. 17-20 1997. Google ScholarDigital Library
- 13.P. Lieverse, P. van der Wolf, E. Deprettere, and K. Vissers. A methodology for architecture exploration of heterogeneous signal processing systems. In Proceedings of the 1999 IEEE Workshop in Signal Processing Systems, Taipei, Taiwan, 1999.Google Scholar
- 14.P. Quinton, S. Rajopadhye, and T. Risset. On Manipulating 7/,- polyhedra. Technical report, Institut de Recherche en Informatique et Systbmes Aldatoires, 1996.Google Scholar
- 15.E. Rijpkema, E. F. Deprettere, and G. Hekstra. A strategy for determining a jacobi specific dataflow processor. In Proceedings ASAP' 97 conference, July 1997. Google ScholarDigital Library
- 16.S.Y. Kung. VLSI Array Processors. Prentice Hall Information and System Sciences Series, 1988. Google ScholarDigital Library
- 17.L. Thiele. Resource constrained scheduling of uniform algorithms. In Conference on Application Specific Array Processors, volume 20, pages 29-40, October 1993.Google ScholarCross Ref
Index Terms
- Compaan: deriving process networks from Matlab for embedded signal processing architectures
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