Ghasem Pasandi
Massoud Pedram
ABSTRACT
This paper aims at integrating three powerful techniques namely Deep Learning, Approximate Computing, and Low Power Design into a strategy to optimize logic at the synthesis level. We utilize advances in deep learning to guide an approximate logic synthesis engine to minimize the dynamic power consumption of a given digital CMOS circuit, subject to a predetermined error rate at the primary outputs. Our framework, Deep-PowerX1, focuses on replacing or removing gates on a technology-mapped network and uses a Deep Neural Network (DNN) to predict error rates at primary outputs of the circuit when a specific part of the netlist is approximated. The primary goal of Deep-PowerX is to reduce the dynamic power whereas area reduction serves as a secondary objective. Using the said DNN, Deep-PowerX is able to reduce the exponential time complexity of standard approximate logic synthesis to linear time. Experiments are done on numerous open source benchmark circuits. Results show significant reduction in power and area by up to 1.47× and 1.43× compared to exact solutions and by up to 22% and 27% compared to state-of-the-art approximate logic synthesis tools while having orders of magnitudes lower run-time.
Supplemental Material
- Jingwei Huang et al. A surface approximation method for image and video correspondences. IEEE Tran. on Ima. Proc., 24(12):5100--5113, 2015.Google Scholar
Digital Library
- Gyan Ranjan et al. Approximate matching of persistent lexicon using search-engines for classifying mobile app traffic. In The 35th Annu. IEEE Inter. Conf. on Comp. Com. (INFOCOM), pages 1--9. IEEE, 2016.Google Scholar
- Kai-Hsiang Yang et al. Approximate search engine optimization for directory service. In Proc. Inter. Paral. and Dist. Proc. Symp., pages 8-pp. IEEE, 2003.Google Scholar
- Yann LeCun, Yoshua Bengio, and Geoffrey Hinton. Deep learning. nature, 521(7553):436--444, 2015.Google Scholar
- Alex Krizhevsky, Ilya Sutskever, and Geoffrey E Hinton. Imagenet classification with deep convolutional neural networks. In Adv. in neur. info. proc. sys., pages 1097--1105, 2012.Google Scholar
- Mahdi Nazemi, Ghasem Pasandi, and Massoud Pedram. Energy-efficient, low-latency realization of neural networks through boolean logic minimization. In 24th Asi. Sou. Pacif. Desi. Auto. Conf. (ASP-DAC), pages 1--6. IEEE, 2019.Google ScholarDigital Library
- Nasir Mohyuddin, Ehsan Pakbaznia, and Massoud Pedram. Probabilistic error propagation in a logic circuit using the boolean difference calculus. In Adv. Tech. in Logi. Syn., Opt. Appl., pages 359--381. Springer, 2011.Google Scholar
- Yi Wu and Weikang Qian. An efficient method for multi-level approximate logic synthesis under error rate constraint. In Proc. of the 53rd Ann. Desi. Auto. Conf. (DAC). ACM, 2016.Google ScholarDigital Library
- S. Hashemi, H. Tann, and S. Reda. Blasys: Approximate logic synthesis using boolean matrix factorization. In 55th ACM/IEEE Desi. Auto. Conf. (DAC), June 2018.Google ScholarDigital Library
- Z. Zhou et al. Dals: Delay-driven approximate logic synthesis. In IEEE/ACM Inter. Conf. on Comp.-Aid. Desi. (ICCAD), pages 1--7, Nov 2018.Google Scholar
- Swagath Venkataramani et al. Substitute-and-simplify: A unified design paradigm for approximate and quality configurable circuits. In Proc. of Conf. on Des., Auto. Test in Euro., pages 1367--1372, 2013.Google Scholar
- J. Schlachter et al. Design and applications of approximate circuits by gate-level pruning. IEEE Tran. on Ver. Larg. Sca. Int. (VLSI) Sys., 25(5):1694--1702, May 2017.Google Scholar
- G. Zervakis et al. Vader: Voltage-driven netlist pruning for cross-layer approximate arithmetic circuits. IEEE Tran. on Ver. Larg. Sca. Int. (VLSI) Sys., 27(6):1460--1464, June 2019.Google Scholar
- Ghasem Pasandi, Shahin Nazarian, and Massoud Pedram. Approximate logic synthesis: A reinforcement learning-based technology mapping approach. In 20th Inter. Symp. on Qual. Elec. Desi. (ISQED), pages 26--32. IEEE, 2019.Google ScholarCross Ref
- Cunxi Yu, Houping Xiao, and Giovanni De Micheli. Developing synthesis flows without human knowledge. In Proc. of the 55th Ann. Desi. Auto. Conf. (DAC), 2018.Google ScholarDigital Library
- Abdelrahman Hosny et al. Drills: Deep reinforcement learning for logic synthesis. arXiv preprint arXiv:1911.04021, 2019.Google Scholar
- Stephen Jang et al. A power optimization toolbox for logic synthesis and mapping. 2009.Google Scholar
- Sasan Iman and Massoud Pedram. Logic synthesis for low power VLSI designs. Springer Science & Business Media, 1998.Google ScholarCross Ref
- Alan Mishchenko et al. ABC: A system for sequential synthesis and verification. Berkeley Logic Synthesis and Verification Group, 2018.Google Scholar
- Arisona State University. Predictive technology model (ptm), 2013.Google Scholar
- F. Brglez and H. Fujiwara. A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran. In ISCAS 85, pages 677--692. IEEE Press, Piscataway, N.J., 1985.Google Scholar
- Saeyang Yang. Logic synthesis and optimization benchmarks user guide: version 3.0. Microelectronics Center of North Carolina (MCNC), 1991.Google Scholar
- Luca Amaru et. al. The EPFL combinational benchmark suite, 2017.Google Scholar
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