ABSTRACT
Phase change memory (PCM) is a scalable non-volatile memory technology that has low access latency (like DRAM) and high capacity (like Flash). Writing to PCM incurs significantly higher latency and energy penalties compared to reading its content. A prominent characteristic of PCM’s write operation is that its latency and energy are sensitive to the data to be written as well as the content that is overwritten. We observe that overwriting unknown memory content can incur significantly higher latency and energy compared to overwriting known all-zeros or all-ones content. This is because all-zeros or all-ones content is overwritten by programming the PCM cells only in one direction, i.e., using either SET or RESET operations, not both.
In this paper, we propose data content aware PCM writes (DATACON), a new mechanism that reduces the latency and energy of PCM writes by redirecting these requests to overwrite memory locations containing all-zeros or all-ones. DATACON operates in three steps. First, it estimates how much a PCM write access would benefit from overwriting known content (e.g., all-zeros, or all-ones) by comprehensively considering the number of set bits in the data to be written, and the energy-latency trade-offs for SET and RESET operations in PCM. Second, it translates the write address to a physical address within memory that contains the best type of content to overwrite, and records this translation in a table for future accesses. We exploit data access locality in work- loads to minimize the address translation overhead. Third, it re-initializes unused memory locations with known all- zeros or all-ones content in a manner that does not interfere with regular read and write accesses. DATACON overwrites unknown content only when it is absolutely necessary to do so. We evaluate DATACON with workloads from state- of-the-art machine learning applications, SPEC CPU2017, and NAS Parallel Benchmarks. Results demonstrate that DATACON improves the effective access latency by 31%, overall system performance by 27%, and total memory system energy consumption by 43% compared to the best of performance-oriented state-of-the-art techniques.
- “TensorFlow models and datasets,” https://www.tensorflow.org /resources/models-datasets, 2020.Google Scholar
- J. Ahn, S. Hong, S. Yoo, O. Mutlu, and K. Choi, “A scalable processingin-memory accelerator for parallel graph processing,” in ISCA, 2015.Google ScholarDigital Library
- J. Ahn, S. Yoo, O. Mutlu, and K. Choi, “PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture,” in ISCA, 2015.Google ScholarDigital Library
- Improving Phase Change Memory Performance with Data Content Aware Access ISMM ’20, June 16, 2020, London, UKGoogle Scholar
- S. J. Ahn, Y. N. Hwang, Y. J. Song, S. H. Lee, S. Y. Lee, J. H. Park, C. W. Jeong, K. C. Ryoo, J. M. Shin, Y. Fai, J. H. Oh, G. H. Koh, G. T. Jeong, S. H. Joo, S. H. Choi, Y. H. Son, J. C. Shin, Y. T. Kim, H. S. Jeong, and Kinam Kim, “Highly reliable 50nm contact cell technology for 256Mb PRAM,” in VLSI Technology, 2005.Google Scholar
- H. Akinaga and H. Shima, “Resistive random access memory (ReRAM) based on metal oxides,” Proceedings of the IEEE, 2010.Google ScholarCross Ref
- M. Alshboul, J. Tuck, and Y. Solihin, “Lazy persistency: A highperforming and write-efficient software persistency technique,” in ISCA, 2018.Google Scholar
- G. Atwood, “PCM applications and an outlook to the future,” in Phase Change Memory, 2018.Google ScholarCross Ref
- A. Awad, Y. Wang, D. Shands, and Y. Solihin, “Obfusmem: A lowoverhead access obfuscation for trusted memories,” in ISCA, 2017.Google Scholar
- A. Awad, M. Ye, Y. Solihin, L. Njilla, and K. A. Zubair, “Triad-NVM: Persistency for integrity-protected and encrypted non-volatile memories,” in ISCA, 2019.Google Scholar
- D. Bailey, E. Barszcz, J. Barton, D. Browning, R. Carter, L. Dagum, R. Fatoohi, P. Frederickson, T. Lasinski, R. Schreiber, H. Simon, V. Venkatakrishnan, and S. Weeratunga, “The NAS parallel benchmarks,” Supercomputing Applications, 1991.Google ScholarDigital Library
- R. Bez, “Chalcogenide PCM: A memory technology for next decade,” in IEDM, 2009.Google ScholarCross Ref
- S. Bock, B. Childers, R. Melhem, D. Mosse, and Y. Zhang, “Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory,” in ISPASS, 2011.Google ScholarDigital Library
- S. Bock, B. R. Childers, R. Melhem, and D. Mossé, “Concurrent page migration for mobile systems with OS-managed hybrid memory,” in CF, 2014.Google Scholar
- S. Bock, B. R. Childers, R. Melhem, and D. Mossé, “Characterizing the overhead of software-managed hybrid main memory,” in MASCOTS, 2015.Google ScholarDigital Library
- S. Bock, B. R. Childers, R. Melhem, and D. Mosse, “HMMSim: A simulator for hardware-software co-design of hybrid main memory,” in NVMSA, 2015.Google ScholarCross Ref
- S. Bock, B. R. Childers, R. Melhem, and D. Mossé, “Understanding the limiting factors of page migration in hybrid main memory,” in CF, 2015.Google Scholar
- S. Bock, B. R. Childers, R. Melhem, and D. Mossé, “Concurrent migration of multiple pages in software-managed hybrid main memory,” in ICCD, 2016.Google ScholarCross Ref
- D. Bondurant, “Ferroelectronic RAM memory family for critical data storage,” Ferroelectrics, 1990.Google Scholar
- A. Boroumand, S. Ghose, M. Patel, H. Hassan, B. Lucia, K. Hsieh, K. T. Malladi, H. Zheng, and O. Mutlu, “LazyPIM: An efficient cache coherence mechanism for processing-in-memory,” CAL, 2016.Google Scholar
- A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan et al., “Google workloads for consumer devices: Mitigating data movement bottlenecks,” in ASPLOS, 2018.Google ScholarDigital Library
- K. Bourzac, “Has Intel created a universal memory technology?” Spectrum, 2017.Google ScholarDigital Library
- J. Bucek, K.-D. Lange, and J. v. Kistowski, “SPEC CPU2017: Nextgeneration compute benchmark,” in ICPE, 2018.Google ScholarDigital Library
- G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy, “Overview of candidate device technologies for storage-class memory,” IBM JRD, 2008.Google ScholarDigital Library
- G. W. Burr, M. J. Breitwisch, M. Franceschini, D. Garetto, K. Gopalakrishnan, B. Jackson, B. Kurdi, C. Lam, L. A. Lastras, A. Padilla, B. Rajendran, S. Raoux, and R. S. Shenoy, “Phase change memory technology,” Vacuum Science & Technology B, 2010.Google Scholar
- Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo, and O. Mutlu, “Error characterization, mitigation, and recovery in flash-memory-based solid-state drives,” Proceedings of the IEEE, 2017.Google ScholarCross Ref
- K. Chandrasekar, C. Weis, Y. Li, B. Akesson, N. Wehn, and K. Goossens, “DRAMPower: Open-source DRAM power & energy estimation tool,” http://www. drampower. info, 2012.Google Scholar
- K. K. Chang, A. G. Yağlıkçı, S. Ghose, A. Agrawal, N. Chatterjee, A. Kashyap, D. Lee, M. O’Connor, H. Hassan, and O. Mutlu, “Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms,” SIGMETRICS, 2017.Google ScholarDigital Library
- L.-P. Chang, T.-W. Kuo, and S.-W. Lo, “Real-time garbage collection for flash-memory storage systems of real-time embedded systems,” TECS, 2004.Google ScholarDigital Library
- C. Chen, A. Schrott, M. H. Lee, S. Raoux, Y. H. Shih, M. Breitwisch, F. H. Baumann, E. K. Lai, T. M. Shaw, P. Flaitz, R. Cheek, E. A. Joseph, S. H. Chen, B. Rajendran, H. L. Lung, and C. Lam, “Endurance improvement of Ge2Sb2Te5-based phase change memory,” in IMW, 2009.Google ScholarCross Ref
- J. Chen, Z. Winter, G. Venkataramani, and H. H. Huang, “rpram: Exploring redundancy techniques to improve lifetime of PCM-based main memory,” in PACT, 2011.Google ScholarDigital Library
- J. Chen, R. C. Chiang, H. H. Huang, and G. Venkataramani, “Energyaware writes to non-volatile main memory,” OSR, 2012.Google Scholar
- S. Chhabra and Y. Solihin, “i-NVMM: A secure non-volatile main memory system with incremental encryption,” in ISCA, 2011.Google Scholar
- S. Cho and H. Lee, “Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance,” in MICRO, 2009.Google ScholarDigital Library
- J. Collins, S. Sair, B. Calder, and D. M. Tullsen, “Pointer cache assisted prefetching,” in MICRO, 2002.Google ScholarDigital Library
- G. Dhiman, R. Ayoub, and T. Rosing, “PDRAM: A hybrid PRAM and DRAM main memory system,” in DAC, 2009.Google ScholarDigital Library
- H. Dogan, F. Hijaz, M. Ahmad, B. Kahne, P. Wilson, and O. Khan, “Accelerating graph and machine learning workloads using a shared memory multicore architecture with auxiliary support for inhardware explicit messaging,” in IPDPS, 2017.Google Scholar
- Y. Du, M. Zhou, B. R. Childers, D. Mossé, and R. Melhem, “Bit mapping for balanced PCM cell programming,” in ISCA, 2013.Google Scholar
- E. Ebrahimi, O. Mutlu, and Y. N. Patt, “Techniques for bandwidthefficient prefetching of linked data structures in hybrid prefetching systems,” in HPCA, 2009.Google ScholarCross Ref
- Y. Fang, H. Li, and X. Li, “SoftPCM: Enhancing energy efficiency and lifetime of phase change memory in video applications via approximate write,” in ATS, 2012.Google ScholarDigital Library
- A. P. Ferreira, M. Zhou, S. Bock, B. Childers, R. Melhem, and D. Mossé, “Increasing PCM main memory lifetime,” in DATE, 2010.Google ScholarDigital Library
- P. Frigo, E. Vannacci, H. Hassan, V. van der Veen, O. Mutlu, C. Giuffrida, H. Bos, and K. Razavi, “TRRespass: Exploiting the Many Sides of Target Row Refresh,” S&P, 2020.Google Scholar
- S. Gueron, “Memory encryption for general-purpose processors,” S&P, 2016.Google Scholar
- J. Guerra, L. Mármol, D. Campello, C. Crespo, R. Rangaswami, and J. Wei, “Software persistent memory,” in ATC, 2012.Google ScholarDigital Library
- A. Gupta, Y. Kim, and B. Urgaonkar, “DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings,” in ASPLOS, 2009.Google ScholarDigital Library
- T. J. Ham, B. K. Chelepalli, N. Xue, and B. C. Lee, “Disintegrated control for energy-efficient and heterogeneous memory systems,” in HPCA, 2013.Google Scholar
- M. Hashemi, Khubaib, E. Ebrahimi, O. Mutlu, and Y. N. Patt, “Accelerating dependent cache misses with an enhanced memory controller,” in ISCA, 2016.Google Scholar
- M. Henson and S. Taylor, “Memory encryption: A survey of existing techniques,” CSUR, 2014.Google ScholarDigital Library
- J.-W. Hsieh and Y.-H. Kuan, “Double circular caching scheme for DRAM/PRAM hybrid cache,” in RTCSA, 2012.Google ScholarDigital Library
- K. Hsieh, S. Khan, N. Vijaykumar, K. K. Chang, A. Boroumand, S. Ghose, and O. Mutlu, “Accelerating pointer chasing in 3D-stacked ISMM ’20, June 16, 2020, London, UK Shihao Song, Anup Das, Onur Mutlu, and Nagarajan Kandasamy memory: Challenges, mechanisms, evaluation,” in ICCD, 2016.Google Scholar
- J. Hu, C. J. Xue, Q. Zhuge, W.-C. Tseng, and E. H.-M. Sha, “Write activity reduction on non-volatile main memories for embedded chip multiprocessors,” TECS, 2013.Google ScholarDigital Library
- Y. Huang, T. Liu, and C. J. Xue, “Register allocation for write activity minimization on non-volatile main memory,” in ASP-DAC, 2011.Google ScholarCross Ref
- W. Hwang and K. H. Park, “Hmmsched: Hybrid main memory-aware task scheduling on multicore systems,” in Future Computing, 2013.Google Scholar
- D. H. Im, J. I. Lee, S. L. Cho, H. G. An, D. H. Kim, I. S. Kim, H. Park, D. H. Ahn, H. Horii, S. O. Park, U. Chung, and J. T. Moon, “A unified 7.5nm dash-type confined cell for high performance PRAM device,” in IEDM, 2008.Google ScholarCross Ref
- A. N. Jacobvitz, R. Calderbank, and D. J. Sorin, “Coset coding to extend the lifetime of memory,” in HPCA, 2013.Google ScholarDigital Library
- Y. Jia, F. Zhou, X. Gao, S. Wu, H. Jin, X. Liao, and P. Yuan, “VAIL: A victim-aware cache policy for improving lifetime of hybrid memory,” Parallel Computing, 2018.Google Scholar
- L. Jiang, Y. Zhang, B. R. Childers, and J. Yang, “FPB: Fine-grained power budgeting to improve write throughput of multi-level cell phase change memory,” in MICRO, 2012.Google ScholarDigital Library
- L. Jiang, Y. Du, B. Zhao, Y. Zhang, B. R. Childers, and J. Yang, “Hardware-assisted cooperative integration of wear-leveling and salvaging for phase change memory,” TACO, 2013.Google ScholarDigital Library
- L. Jiang, Y. Zhang, and J. Yang, “Mitigating write disturbance in superdense phase change memories,” in DSN, 2014.Google Scholar
- S. H. Jo and W. Lu, “CMOS compatible nanoscale nonvolatile resistance switching memory,” Nano Letters, 2008.Google ScholarCross Ref
- Y. Joo, D. Niu, X. Dong, G. Sun, N. Chang, and Y. Xie, “Energy-and endurance-aware design of phase change memory caches,” in DATE, 2010.Google Scholar
- M. J. Kang, T. J. Park, Y. W. Kwon, D. H. Ahn, Y. S. Kang, H. Jeong, S. J. Ahn, Y. J. Song, B. C. Kim, S. W. Nam, H. K. Kang, G. T. Jeong, and C. H. Chung, “PRAM cell technology and characterization in 20nm node size,” in IEDM, 2011.Google ScholarCross Ref
- U. Kang, H.-s. Yu, C. Park, H. Zheng, J. Halbert, K. Bains, S. Jang, and J. S. Choi, “Co-architecting controllers and DRAM to enhance DRAM process scaling,” in The Memory Forum, 2014.Google Scholar
- S. Kannan, M. Qureshi, A. Gavrilovska, and K. Schwan, “Energy aware persistence: Reducing energy overheads of memory-based persistence in NVMs,” in PACT, 2016.Google ScholarDigital Library
- M. Karlsson, F. Dahlgren, and P. Stenstrom, “A prefetching technique for irregular accesses to linked data structures,” in HPCA, 2000.Google Scholar
- J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho, “A space-efficient flash translation layer for CompactFlash systems,” TCE, 2002.Google Scholar
- Y. Kim, V. Seshadri, D. Lee, J. Liu, and O. Mutlu, “A case for exploiting subarray-level parallelism (SALP) in DRAM,” in ISCA, 2012.Google ScholarDigital Library
- Y. Kim, R. Daly, J. Kim, C. Fallin, J. H. Lee, D. Lee, C. Wilkerson, K. Lai, and O. Mutlu, “Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors,” in ISCA, 2014.Google ScholarDigital Library
- Y. Kim, W. Yang, and O. Mutlu, “Ramulator: A fast and extensible DRAM simulator.” CAL, 2016.Google ScholarDigital Library
- N. Kohout, S. Choi, D. Kim, and D. Yeung, “Multi-chain prefetching: Effective exploitation of inter-chain memory parallelism for pointerchasing codes,” in PACT, 2001.Google ScholarCross Ref
- E. Kültürsay, M. Kandemir, A. Sivasubramaniam, and O. Mutlu, “Evaluating STT-RAM as an energy-efficient main memory alternative,” in ISPASS, 2013.Google ScholarCross Ref
- M. Kund, G. Beitel, C.-U. Pinnow, T. Rohr, J. Schumann, R. Symanczyk, K. Ufert, and G. Muller, “Conductive bridging RAM (CBRAM): An emerging non-volatile memory technology scalable to sub 20nm,” in IEDM, 2005.Google ScholarCross Ref
- S. Lai, “Current status of the phase change memory and its future,” in IEDM, 2003.Google ScholarCross Ref
- S. Lai, “Non-volatile memory technologies: The quest for ever lower cost,” in IEDM, 2008.Google ScholarCross Ref
- A. Lalam and A. C. Shen, “Non-volatile dual in-line memory module (NVDIMM) multichip package,” US Patent 10,199,364, 2019.Google Scholar
- C. H. Lam and H.-L. Lung, “Block erase for phase change memory,” in US Patent 7,755,935, 2010.Google Scholar
- B. C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. Burger, “Phase-change technology and the future of main memory,” IEEE Micro, 2010.Google ScholarDigital Library
- B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, “Architecting phase change memory as a scalable DRAM alternative,” in ISCA, 2009.Google ScholarDigital Library
- B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, “Phase change memory architecture and the quest for scalability,” CACM, 2010.Google ScholarDigital Library
- C. J. Lee, V. Narasiman, E. Ebrahimi, O. Mutlu, and Y. N. Patt, “DRAMaware last-level cache writeback: Reducing write-caused interference in memory systems,” 2010.Google Scholar
- J. I. Lee, H. Park, S. L. Cho, Y. L. Park, B. J. Bae, J. H. Park, J. S. Park, H. G. An, J. S. Bae, D. H. Ahn, Y. T. Kim, H. Horii, S. A. Song, J. C. Shin, S. O. Park, H. S. Kim, U. Chung, J. T. Moon, and B. I. Ryu, “Highly scalable phase change memory with CVD GeSbTe for sub 50nm generation,” in VLSI Technology, 2007.Google Scholar
- Y. Li, S. Ghose, J. Choi, J. Sun, H. Wang, and O. Mutlu, “Utility-based hybrid memory management,” in CLUSTER, 2017.Google ScholarCross Ref
- Y. Y. Lin, H. B. Lv, P. Zhou, M. Yin, F. F. Liao, Y. F. Cai, T. A. Tang, J. Feng, Y. Zhang, Z. F. Zhang, B. W. Qiao, Y. F. Lai, B. C. Cai, and B. Chen, “Nano-crystalline phase change memory with composite Si-Sb-Te film for better data retention and lower operation current,” in NVSMW, 2007.Google ScholarCross Ref
- S. Liu, A. Kolli, J. Ren, and S. Khan, “Crash consistency in encrypted non-volatile main memory systems,” in HPCA, 2018.Google ScholarCross Ref
- Y. Lu, J. Shu, L. Sun, and O. Mutlu, “Loose-ordering consistency for persistent memory,” in ICCD, 2014.Google ScholarCross Ref
- C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood, “Pin: Building customized program analysis tools with dynamic instrumentation,” in PLDI, 2005.Google ScholarDigital Library
- H. Lung, C. P. Miller, C. Chen, S. C. Lewis, J. Morrish, T. Perri, R. C. Jordan, H. Ho, T. Chen, W. Chien, M. Drapa, T. Maffitt, J. Heath, Y. Nakamura, J. Okazawa, K. Hosokawa, M. BrightSky, R. Bruce, H. Cheng, A. Ray, Y. Ho, C. Yeh, W. Kim, S. Kim, Y. Zhu, and C. Lam, “A double-data-rate 2 (DDR2) interface phase-change memory with 533MB/s read-write data rate and 37.5ns access latency for memorytype storage class memory applications,” in IMW, 2016.Google ScholarCross Ref
- D. Ma, J. Feng, and G. Li, “A survey of address translation technologies for flash memories,” CSUR, 2014.Google ScholarDigital Library
- A. Mallik, D. Garbin, A. Fantini, D. Rodopoulos, R. Degraeve, J. Stuijt, A. K. Das, S. Schaafsma, P. Debacker, G. Donadio, H. Hody, L. Goux, G. S. Kar, A. Furnemont, A. Mocuta, and P. Raghavan, “Designtechnology co-optimization for OxRRAM-based synaptic processing unit,” in VLSI Technology, 2017.Google Scholar
- J. A. Mandelman, R. H. Dennard, G. B. Bronner, J. K. DeBrosse, R. Divakaruni, Y. Li, and C. J. Radens, “Challenges and future directions for the scaling of dynamic random-access memory (DRAM),” IBM JRD, 2002.Google ScholarDigital Library
- V. J. Marathe, M. Seltzer, S. Byan, and T. Harris, “Persistent memcached: Bringing legacy code to byte-addressable persistent memory,” in HotStorage, 2017.Google Scholar
- J. Meza, J. Chang, H. Yoon, O. Mutlu, and P. Ranganathan, “Enabling efficient and scalable hybrid memories using fine-granularity DRAM cache management,” CAL, 2012.Google ScholarDigital Library
- J. Meza, Y. Luo, S. Khan, J. Zhao, Y. Xie, and O. Mutlu, “A case for efficient hardware/software cooperative management of storage and memory,” in WEED, 2013.Google Scholar
- A. Mirhoseini, M. Potkonjak, and F. Koushanfar, “Coding-based energy minimization for phase change memory,” in DAC, 2012.Google ScholarDigital Library
- T. Morikawa, K. Kurotsuchi, M. Kinoshita, N. Matsuzaki, Y. Matsui, Y. Fujisaki, S. Hanzawa, A. Kotabe, M. Terao, H. Moriya, T. Iwasaki, Improving Phase Change Memory Performance with Data Content Aware Access ISMM ’20, June 16, 2020, London, UK M. Matsuoka, F. Nitta, M. Moniwa, T. Koga, and N. Takaura, “Doped In-Ge-Te phase change memory featuring stable operation and good data retention,” in IEDM, 2007.Google Scholar
- O. Mutlu, “Memory scaling: A systems architecture perspective,” in IMW, 2013.Google ScholarCross Ref
- O. Mutlu, “The RowHammer problem and other issues we may face as memory becomes denser,” in DATE, 2017.Google ScholarDigital Library
- O. Mutlu and J. S. Kim, “Rowhammer: A retrospective,” TCAD, 2019.Google ScholarDigital Library
- O. Mutlu and L. Subramanian, “Research problems and opportunities in memory systems,” Supercomputing Frontiers and Innovations, 2015.Google Scholar
- L. Nai, R. Hadidi, J. Sim, H. Kim, P. Kumar, and H. Kim, “Graphpim: Enabling instruction-level pim offloading in graph computing frameworks,” in HPCA, 2017.Google ScholarCross Ref
- J. H. Oh, J. H. Park, Y. S. Lim, H. S. Lim, Y. T. Oh, J. S. Kim, J. M. Shin, J. H. Park, Y. J. Song, K. C. Ryoo, D. W. Lim, S. S. Park, J. I. Kim, J. H. Kim, J. Yu, F. Yeung, C. W. Jeong, J. H. Kong, D. H. Kang, G. H. Koh, G. T. Jeong, H. S. Jeong, and K. Kim, “Full integration of highly manufacturable 512Mb PRAM based on 90nm technology,” in IEDM, 2006.Google ScholarCross Ref
- S. R. Ovshinsky, “Reversible electrical switching phenomena in disordered structures,” PRL, 1968.Google ScholarCross Ref
- L. Peled, U. Weiser, and Y. Etsion, “A neural network prefetcher for arbitrary memory access patterns,” TACO, 2019.Google ScholarDigital Library
- A. Pirovano, A. Redaelli, F. Pellizzer, F. Ottogalli, M. Tosi, D. Ielmini, A. L. Lacaita, and R. Bez, “Reliability study of phase-change nonvolatile memories,” TDMR, 2004.Google ScholarCross Ref
- M. Poremba, T. Zhang, and Y. Xie, “Nvmain 2.0: A user-friendly memory simulator to model (non-) volatile memory systems,” CAL, 2015.Google ScholarDigital Library
- B. Pourshirazi, M. V. Beigi, Z. Zhu, and G. Memik, “WALL: A writeback-aware LLC management for PCM-based main memory systems,” in DATE, 2018.Google Scholar
- M. K. Qureshi, “Pay-As-You-Go: Low-overhead hard-error correction for phase change memories,” in MICRO, 2011.Google ScholarDigital Library
- M. K. Qureshi, V. Srinivasan, and J. A. Rivers, “Scalable high performance main memory system using phase-change memory technology,” in ISCA, 2009.Google ScholarDigital Library
- M. K. Qureshi, M. M. Franceschini, L. A. Lastras-Montaño, and J. P. Karidis, “Morphable memory system: A robust architecture for exploiting multi-level phase change memories,” in ISCA, 2010.Google Scholar
- M. K. Qureshi, M. M. Franceschini, and L. A. Lastras-Montano, “Improving read performance of phase change memories via write cancellation and write pausing,” in HPCA, 2010.Google ScholarCross Ref
- M. K. Qureshi, M. M. Franceschini, A. Jagmohan, and L. A. Lastras, “PreSET: Improving performance of phase change memories by exploiting asymmetry in write times,” in ISCA, 2012.Google ScholarDigital Library
- J. Ren, J. Zhao, S. Khan, J. Choi, Y. Wu, and O. Mutiu, “ThyNVM: Enabling software-transparent crash consistency in persistent memory systems,” in MICRO, 2015.Google ScholarDigital Library
- S. K. Sadasivam, B. W. Thompto, R. Kalla, and W. J. Starke, “IBM Power9 processor architecture,” IEEE Micro, 2017.Google ScholarDigital Library
- G. Saileshwar, P. Nair, P. Ramrakhyani, W. Elsasser, J. Joao, and M. Qureshi, “Morphable counters: Enabling compact integrity trees for low-overhead secure memories,” in MICRO, 2018.Google ScholarDigital Library
- G. Saileshwar, P. J. Nair, P. Ramrakhyani, W. Elsasser, and M. K. Qureshi, “Synergy: Rethinking secure-memory design for errorcorrecting memories,” in HPCA, 2018.Google Scholar
- M. Salinga, B. Kersting, I. Ronneberger, V. P. Jonnalagadda, X. T. Vu, M. Le Gallo, I. Giannopoulos, O. Cojocaru-Mirédin, R. Mazzarello, and A. Sebastian, “Monatomic phase change memory,” Nature Materials, 2018.Google ScholarCross Ref
- A. Sebastian, T. Tuma, N. Papandreou, M. Le Gallo, L. Kull, T. Parnell, and E. Eleftheriou, “Temporal correlation detection using computational phase-change memory,” Nature Communications, 2017.Google ScholarCross Ref
- J. Secco, F. Corinto, and A. Sebastian, “Flux–charge memristor model for phase change memory,” TCAS II: Express Briefs, 2018.Google ScholarCross Ref
- N. H. Seong, D. H. Woo, and H.-H. S. Lee, “Security Refresh: Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping,” in ISCA, 2010.Google Scholar
- V. Seshadri, A. Bhowmick, O. Mutlu, P. B. Gibbons, M. A. Kozuch, and T. C. Mowry, “The dirty-block index,” in ISCA, 2014.Google ScholarDigital Library
- L. Song, Y. Zhuo, X. Qian, H. Li, and Y. Chen, “GraphR: Accelerating graph processing using ReRAM,” in HPCA, 2018.Google ScholarCross Ref
- S. Song, A. Das, O. Mutlu, and N. Kandasamy, “Enabling and exploiting partition-level parallelism (PALP) in phase change memories,” TECS, 2019.Google ScholarDigital Library
- J. Stuecheli, D. Kaseridis, D. Daly, H. C. Hunter, and L. K. John, “The virtual write queue: Coordinating DRAM and last-level cache policies,” in ISCA, 2010.Google Scholar
- S. Swami, J. Rakshit, and K. Mohanram, “Secret: Smartly encrypted energy efficient non-volatile memories,” in DAC, 2016.Google ScholarDigital Library
- C. Villa, “PCM array architecture and management,” in Phase Change Memory, 2018.Google ScholarCross Ref
- C. Villa, D. Mills, G. Barkley, H. Giduturi, S. Schippers, and D. Vimercati, “A 45nm 1Gb 1.8 V phase-change memory,” in ISSCC, 2010.Google Scholar
- H. Volos, A. J. Tack, and M. M. Swift, “Mnemosyne: Lightweight persistent memory,” in ASPLOS, 2011.Google ScholarDigital Library
- R. Wang, L. Jiang, Y. Zhang, L. Wang, and J. Yang, “Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory,” in DAC, 2015.Google ScholarDigital Library
- Y. Wang, Y. Zheng, G. Liu, T. Li, T. Guo, Y. Cheng, S. Lv, S. Song, K. Ren, and Z. Song, “Scandium doped Ge2Sb2Te5 for high-speed and low-power-consumption phase change memory,” APL, 2018.Google Scholar
- Z. Wang, S. Shan, T. Cao, J. Gu, Y. Xu, S. Mu, Y. Xie, and D. A. Jiménez, “WADE: Writeback-aware dynamic cache management for NVMbased main memory system,” TACO, 2013.Google ScholarDigital Library
- Z. Wang and T. Nowatzki, “Stream-based memory access specialization for general purpose processors,” in ISCA, 2019.Google Scholar
- M. V. Wilkes, “The memory gap and the future of high performance memories,” Computer Architecture News, 2001.Google ScholarDigital Library
- H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson, “Phase change memory,” Proceedings of the IEEE, 2010.Google ScholarCross Ref
- H.-S. P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, B. Lee, F. T. Chen, and M.-J. Tsai, “Metal–oxide RRAM,” Proceedings of the IEEE, 2012.Google ScholarCross Ref
- M. Wuttig and N. Yamada, “Phase-change materials for rewriteable data storage,” Nature Materials, 2007.Google Scholar
- F. Xia, D. Jiang, J. Xiong, M. Chen, L. Zhang, and N. Sun, “DWC: Dynamic write consolidation for phase change memory systems,” in ICS, 2014.Google ScholarDigital Library
- N. Yamada, R. Kojima, T. Nishihara, A. Tsuchino, Y. Tomekawa, and H. Kusada, “100GB rewritable triple-layer optical disk having Ge-Sb-Te films,” in Phase-Change and Ovonics Symposium, 2009.Google Scholar
- B.-D. Yang, J.-E. Lee, J.-S. Kim, J. Cho, S.-Y. Lee, and B.-G. Yu, “A low power phase-change random access memory using a data-comparison write scheme,” in ISCAS, 2007.Google ScholarCross Ref
- J. Yang, L. Gao, and Y. Zhang, “Improving memory encryption performance in secure processors,” TC, 2005.Google Scholar
- M. Ye, C. Hughes, and A. Awad, “Osiris: A low-cost mechanism to enable restoration of secure non-volatile memories,” in MICRO, 2018.Google ScholarDigital Library
- H. Yoon, J. Meza, R. Ausavarungnirun, R. A. Harding, and O. Mutlu, “Row buffer locality aware caching policies for hybrid memories,” in ICCD, 2012.Google ScholarDigital Library
- H. Yoon, J. Meza, N. Muralimanohar, N. P. Jouppi, and O. Mutlu, “Efficient data mapping and buffering techniques for multilevel cell phase-change memories,” TACO, 2014.Google ScholarDigital Library
- J. Yue and Y. Zhu, “Accelerating write by exploiting PCM asymmetries,” in HPCA, 2013.Google Scholar
- ISMM ’20, June 16, 2020, London, UK Shihao Song, Anup Das, Onur Mutlu, and Nagarajan KandasamyGoogle Scholar
- L. Zhang, B. Neely, D. Franklin, D. Strukov, Y. Xie, and F. T. Chong, “Mellow writes: Extending lifetime in resistive memories through selective slow write backs,” in ISCA, 2016.Google Scholar
- T. Zhang, Z. Song, F. Wang, B. Liu, S. Feng, and B. Chen, “Te-free SiSb phase change material for high data retention phase change memory application,” JJAP, 2007.Google ScholarCross Ref
- Y. Zhang, J. Yang, A. Memaripour, and S. Swanson, “Mojim: A reliable and highly-available non-volatile memory system,” in ASPLOS, 2015.Google ScholarDigital Library
- J. Zhao, O. Mutlu, and Y. Xie, “FIRM: Fair and high-performance memory control for persistent memory systems,” in MICRO, 2014.Google ScholarDigital Library
- M. Zhou, Y. Du, B. Childers, R. Melhem, and D. Mossé, “Writebackaware partitioning and replacement for last-level caches in phase change main memory systems,” TACO, 2012.Google Scholar
- M. Zhou, Y. Du, B. R. Childers, R. Melhem, and D. Mosse, “Writebackaware bandwidth partitioning for multi-core systems with PCM,” in PACT, 2013.Google Scholar
- P. Zhou, B. Zhao, J. Yang, and Y. Zhang, “A durable and energy efficient main memory using phase change memory technology,” in ISCA, 2009.Google ScholarDigital Library
Index Terms
- Improving phase change memory performance with data content aware access
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