Chao Zhao
ABSTRACT
In order to solve the power consumption and cost problems caused by the massive nodes of the Internet of things chip, a new sub sampling PLL circuit is proposed in this paper. The circuit uses dynamic double loop technology to solve the harmonic locking problem of sub sampling, uses leakage compensation technology to reduce the capacitance area, and uses high matching sub sampling charge pump technology to reduce spurious. The test results show that when the output frequency is 1920MHz, the RMS jitter is less than 2.5ps, the power consumption is 0.8mW at 0.6V power supply voltage, and the area is only 105μm×95μm, which meets the clock requirements of the Internet of things chip system.
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