Prattay Chowdhury
ABSTRACT
With most VLSI design companies now being fabless it is imperative to develop methods to protect their Intellectual Property (IP). One approach that has become very popular due to its relative simplicity and practicality is logic locking. One of the problems with traditional locking mechanisms is that the locking circuitry is built into the netlist that the VLSI design company delivers to the foundry which has now access to the entire design including the locking mechanism. This implies that they could potentially tamper with this circuitry or reverse engineer it to obtain the locking key. One relatively new approach that has been coined logic locking through omission, or hardware redaction, maps a portion of the design to an embedded FPGA (eFPGA). The bitstream of the eFPGA now acts as the locking key. This new approach has been shown to be more secure as the foundry has no access to the bitstream during the manufacturing stage. The obvious drawbacks are the increase in design complexity and the area and performance overheads associated with the eFPGA. In this work we propose, to the best of our knowledge, the first attack on these type of new locking mechanisms by substituting the exact logic mapped onto the eFPGA by a synthesizable predictive model that replicates the behavior of the exact logic. We show that this approach is applicable in the context of approximate computing where hardware accelerators tolerate certain degree of errors at their outputs. Experimental results show that our proposed approach is very effective finding suitable predictive models while simultaneously reducing the overall power consumption.
- Benjamin Carrion Schafer and Anushree Mahapatra. 2014. S2CBench:Synthesizable SystemC Benchmark Suite. IEEE Embedded Systems Letters 6, 3 (2014), 53–56.Google Scholar
Cross Ref
- B. Carrion Schafer and Z. Wang. 2019. High-Level Synthesis Design Space Exploration: Past, Present and Future. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2019), 1–12.Google Scholar
- R. S. Chakraborty and S. Bhunia. 2009. HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection. IEEE TCAD 28, 10 (Oct 2009), 1493–1502.Google Scholar
- Jianqi Chen 2020. DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY. In DAC. 1–6.Google Scholar
- Jianqi Chen and Benjamin Carrion Schafer. 2021. Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures. In ASP-DAC. 542–547.Google Scholar
- Bo Hu 2019. Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA. In GLSVLSI. 171–176.Google Scholar
- Prashanth Mohan 2021. Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion. In DATE. 1186–1191.Google Scholar
- F. Pedregosa 2011. Scikit-learn: Machine Learning in Python. Journal of Machine Learning Research 12 (2011), 2825–2830.Google ScholarDigital Library
- M. Tanjidur Rahman 2020. Defense-in-depth: A recipe for logic locking to prevail. Integration, the VLSI Journal 72 (Jan 2020), 37–57.Google Scholar
- J. Rajendran 2013. Is split manufacturing secure?. In 2013 DATE. 1259–1264.Google Scholar
- Jeyavijayan Rajendran 2013. Security Analysis of Integrated Circuit Camouflaging. In SIGSAC Conference on Computer & Communications Security(CCS ’13). 709–720.Google Scholar
- J. Rajendran 2015. Fault Analysis-Based Logic Encryption. IEEE Trans. Comput. 64, 2 (Feb 2015), 410–424.Google ScholarDigital Library
- Jarrod A. Roy 2008. EPIC: Ending Piracy of Integrated Circuits. In DATE. 1069–1074.Google Scholar
- Mustafa M. Shihab 2019. Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming. In DATE. 528–533.Google Scholar
- Huanyu Wang, Domenic Forte, Mark M. Tehranipoor, and Qihang Shi. 2017. Probing Attacks on Integrated Circuits: Challenges and Research Opportunities. IEEE Design Test 34, 5 (2017), 63–71.Google ScholarCross Ref
- Q. Xu, T. Mytkowicz, and N. S. Kim. 2016. Approximate Computing: A Survey. IEEE Design Test 33, 1 (Feb 2016), 8–22.Google ScholarCross Ref
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