Supplemental Material
Available for Download
- 1.D.H. Albonesi: "Selective Cache Ways: On Demand Cache Resource Allocation:" 32nd Annual International Conference on Microarehitecture: pages 248-259: 1999. Google ScholarDigital Library
- 2.B. Abali and H. Franke: "Operating System Support for Fast Hardware Compression of Main Memory Contents:" Workshop on Solving the Memory Wall Problem: June 2000.Google Scholar
- 3.C.D. Benveniste: P.A. Franaszek: and J.T. Robinson: "Cache-Memory Interfaces in Compressed Memory Systems:" Workshop on Solving the Memory Wall Problem: June 2000.Google Scholar
- 4.D. Brooks and M. Martonosi: "Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance:" Fifth International Symposium on High-Performance Computer Architecture: Orlando: Florida: January 1999. Google ScholarDigital Library
- 5.K. Ghose: "Reducing Power in Superscalar Processor Caches using Subbanking: Multiple Line Buffers: and Bit Line Segmentation:" International Symposium on Low Power Electronics and Design: pages 70-75: 1999. Google ScholarDigital Library
- 6.N.P. Jouppi: "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers:" 17th Annual International Symposium on Computer Architecture: Seattle: pages 364-373: 1990. Google ScholarDigital Library
- 7.M. Kjelso: M. Gooch: and S. Jones: "Empirical Study of Memory-data: Characteristics and Compressibility:" IEE Computers and Digital Techniques: Vol. 145: No. 1: pages 63-67: January 1998.Google ScholarCross Ref
- 8.J-S. Lee: W-K. Hong: and S-D. Kim: "Design and Evaluation of a Selective Compressed Memory System:" IEEE International Conference on Computer Design: Austin: TX: pages 184-191: October 1999. Google ScholarDigital Library
- 9.C. Lefurgy: P. Bird: I.-C. Chen: and T. Mudge: "Improving Code Density Using Compression Techniques:" 30th Annual ACM/IEEE International Symposium on Microarehitecture: pages 194-203: 1997. Google ScholarDigital Library
- 10.J. Kin: M. Gupta: and W.H. Mangione-Smith: "The Filter Cache: An Energy Efficient Memory Structure:" 30th Annual ACM/IEEE International Symposium on Microarehitecture: pages 184-193: 1997. Google ScholarDigital Library
- 11.D. Kirovski: J. Kin: and W. H. Mangione-Smith: "Procedure Based Program Compression:" 30th Annual ACM/IEEE International Symposium on Microarehitecture: pages 204-217: 1997. Google ScholarDigital Library
- 12.S. Y. Larin: "Exploiting Program Redundancy to Improve Performance: Cost and Power Consumption in Embedded Systems:" Ph.D. thesis: ECE Dept.: North Carolina State Univ.: Raleigh: North Carolina: August 2000. Google ScholarDigital Library
- 13.S. Onder and R. Gupta: "Automatic Generation of Microarchitecture Simulators:" IEEE International Conference on Computer Languages: pages 80-89: Chicago: Illinois: May 1998. Google ScholarDigital Library
- 14.M.D. Powell: S-H. Yang: B. Falsafi: K. Roy: T.N. Vijaykumar: "Gated Vdd: A Circuit Technique to Reduce Leakage in Deep-submicron Cache Memories:" ACM/IEEE International Symposium on Low Power Electronics and Design: 2000. Google ScholarDigital Library
- 15.P. Ranganathan: S. Adve: and N. Jouppi: "Reconfigurable Caches and their Application to Media Processing:" 27th Annual International Symposium on Computer Architecture: Vancouver: British Columbia: Canada: June 2000. Google ScholarDigital Library
- 16.M. Stephenson: J. Babb: and S. Amarasinghe: "Bitwidth Analysis with Application to Silicon Compilation:" ACM SIGPLAN Conference on Programming Language Design and Implementation: Vancouver: British Columbia: Canada: June 2000. Google ScholarDigital Library
- 17.W. Ye: N. Vijaykrishnan: M. Kandemir: and M.J. Irwin: "The Design and Use of Simplepower: A Cycleaccurate Energy Estimation Tool:" 37th Design Automation Conference: Los Angeles: CA: June 2000. Google ScholarDigital Library
- 18.Y. Zhang: J. Yang: and R. Gupta: "Frequent Value Locality and Value-centric Data Cache Design:" The Ninth International Conference on Architectural Support for Programming Languages and Operating Systems: Cambridge: MA: November 2000. Google ScholarDigital Library
Index Terms
- Frequent value compression in data caches
Recommendations
Frequent value locality and value-centric data cache design
Special Issue: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems (ASPLOS '00)By studying the behavior of programs in the SPECint95 suite we observed that six out of eight programs exhibit a new kind of value locality, the frequent value locality, according to which a few values appear very frequently in memory locations and are ...
Opportunistic compression for direct-mapped DRAM caches
MEMSYS '18: Proceedings of the International Symposium on Memory SystemsLarge off-chip DRAM caches offer performance and bandwidth improvements for many systems by bridging the gap between on-chip last level caches and off-chip memories. To avoid the high hit latency resulting from serial DRAM accesses for tags and data, ...
Frequent value locality and value-centric data cache design
ASPLOS IX: Proceedings of the ninth international conference on Architectural support for programming languages and operating systemsBy studying the behavior of programs in the SPECint95 suite we observed that six out of eight programs exhibit a new kind of value locality, the frequent value locality, according to which a few values appear very frequently in memory locations and are ...
Comments