Arifur Rahman
ABSTRACT
In this paper analytical models for predicting interconnect require?ments in field-programmable gate arrays (FPGAs) are presented, and opportunities for 3-D implementation of FPGAs are examined. The analytical models for 2-D FPGAs are calibrated by routing and placement experiments with benchmark circuits and extended to 3-D FPGAs. Based on system-level modeling, we find that in FPGAs with 20K 4-input look-up tables, the reduction in channel width, interconnect delay, and power dissipation can be over 50% by 3-D implementation.
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- Wiring requirement and three-dimensional integration of field-programmable gate arrays
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