skip to main content
10.1145/378239.378551acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
Article

Low-energy intra-task voltage scheduling using static timing analysis

Authors Info & Claims
Published:22 June 2001Publication History

ABSTRACT

We propose an intra-task voltage scheduling algorithm for low-energy hard real-time applications. Based on a static timing analysis technique, the proposed algorithm controls the supply voltage within an individual task boundary. By fully exploiting all the slack times, a scheduled program by the proposed algorithm always complete its execution near the deadline, thus achieving a high energy reduction ratio. In order to validate the effectiveness of the proposed algorithm, we built a software tool that automatically converts a DVS-unaware program into an equivalent low-energy program. Experimental results show that the low-energy version of an MPEG-4 encoder/decoder (converted by the software tool) consumes less than 7$\sim$25% of the original program running on a fixed-voltage system with a power-down mode.

References

  1. 1.T. Burd, T. Pering, A. Stratakos, and R. Brodersen. A dynamic voltage scaled microprocessor system. In Proc. of IEEE International Solid-State Circuits Conference, pages 294-295, 2000.Google ScholarGoogle ScholarCross RefCross Ref
  2. 2.M. Fleischmann. Crusoe power management: reducing the operating power with LongRun. In Proc. of HotChips 12 Symposium, 2000.Google ScholarGoogle Scholar
  3. 3.C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In Proc. of the 16th IEEE Real-Time Systems Symposium, pages 288-297, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. 4.I. Hong, G. Qu, M. Potkonjak, and M. B. Srivastava. Synthesis techniques for low-power hard real-time systems on variable voltage processor. In Proc. of the 19th IEEE Real-Time Systems Symposium, pages 178-187, 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. 5.T. Ishihara and H. Yasuura. Voltage scheduling problem for dynamically variable voltage processors. In Proc. of International Symposium On Low Power Electronics and Design, pages 197-202, 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. 6.S. Lee and T. Sakurai. Run-time voltage hopping for low-power real-time systems. In Proc. of Design Automation Conference, pages 806-809, 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. 7.Y. Lee and C. M. Krishna. Voltage-clock scaling for low energy consumption in real-time embedded systems. In Proc. of the Sixth International Conference on Real-Time Computing Systems and Applications, pages 272-279, 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. 8.S.-S. Lim, Y. H. Bae, G. T. Jang, B.-D. Rhee, S. L. Min, C. Y. Park, H. Shin, K. Park, and C. S. Kim. An accurate worst case timing analysis for RISC processors. IEEE Transactions on Software Engineering, 21(7):593-604, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. 9.T. Okuma, T. Ishihara, and H. Yasuura. Real-time task scheduling for a variable voltage processor. In Proc. of International Symposium On System Synthesis, pages 24-29, 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. 10.T. Sakurai and A. Newton. Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas. IEEE Journal of Solid State Circuits, 25(2):584-594, 1990.Google ScholarGoogle ScholarCross RefCross Ref
  11. 11.Y. Shin and K. Choi. Power conscious fixed priority scheduling for hard real-time systems. In Proc. of Design Automation Conference, pages 134-139, 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. 12.F. Yao, A. Demers, and S. Shenker. A scheduling model for reduced CPU energy. In Proc. of the 36th Annual Symposium on Foundations of Computer Science, pages 374-382, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Low-energy intra-task voltage scheduling using static timing analysis

                      Recommendations

                      Comments

                      Login options

                      Check if you have access through your login credentials or your institution to get full access on this article.

                      Sign in
                      • Published in

                        cover image ACM Conferences
                        DAC '01: Proceedings of the 38th annual Design Automation Conference
                        June 2001
                        863 pages
                        ISBN:1581132972
                        DOI:10.1145/378239

                        Copyright © 2001 ACM

                        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

                        Publisher

                        Association for Computing Machinery

                        New York, NY, United States

                        Publication History

                        • Published: 22 June 2001

                        Permissions

                        Request permissions about this article.

                        Request Permissions

                        Check for updates

                        Qualifiers

                        • Article

                        Acceptance Rates

                        Overall Acceptance Rate1,770of5,499submissions,32%

                        Upcoming Conference

                        DAC '24
                        61st ACM/IEEE Design Automation Conference
                        June 23 - 27, 2024
                        San Francisco , CA , USA

                      PDF Format

                      View or Download as a PDF file.

                      PDF

                      eReader

                      View online with eReader.

                      eReader