ABSTRACT
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. Software design complexity for embedded systems has increased so much that a high-level functional programming paradigm need to be adopted for formal verifiability, maintainability and short time-to-market. We propose a framework for efficiently generating implementation software from a synchronous state machine specification for embedded control systems. The framework is generic enough to allow hardware/software partition for a given architecture platform. It is demonstrated that the logic optimization and simulation techniques can be combined to produce fast execution code for such embedded systems. Specifically, we propose a framework for software synthesis from multi-valued logic, including fast evaluation of logic functions, and scheduling techniques for node execution. Experiments are performed to show the initial results of our algorithms in this framework.
- P. Ashar and S. Malik. Fast functional simulation using branching program. In Proc. of the Intl. Conf. on Computer-Aided Design, pages 408--412, Nov. 1995.]] Google ScholarDigital Library
- F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, E. Sentovich, K. Suzuki, and B.Tabbara. Hardware-Software Co-Design of Embedded Systems: The Polis Approach. Kluwer Academic Press, 1997.]] Google ScholarDigital Library
- F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. L. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki. Synthesis of software programs for embedded control applications. IEEE Trans. Comput.-Aided Design Integrated Circuits, 18(6):834--49, June 1999.]]Google ScholarDigital Library
- M. Baleani, F. Gennari, Y. Jiang, Y. Patel, R. K. Brayton, and A. Sangiovanni-Vincentelli. Hw/sw partitioning and code generation of embedded control applications on a reconfigurable architecture platform. In Proc. of the Intl. Symposium on Hardware/Software Co-Design, May. 2002.]] Google ScholarDigital Library
- G. Berry. Esterel on hardware. Philosophical Transactions of the Royal Society of London. Series A, 1992.]]Google Scholar
- G. Berry. The constructive semantics of pure Esterel. Book in preparation, 1996.]]Google Scholar
- G. Berry and G. Gonthier. The Esterel synchronous programming language: Design, semantics, implementation. Science of Computer Programming, 1992.]] Google ScholarDigital Library
- R. K. Brayton and et al. MVSIS. http://www-cad.eecs.berkeley.edu/mvsis.]]Google Scholar
- K. T. Cheng and A. Krishnakumar. Automatic functional test generation using the extended finite state machine model. In Proc. of the Design Automation Conf., June 1993.]] Google ScholarDigital Library
- S. Edwards. Compiling esterel into sequential code. In Proc. of the Design Automation Conf., June 2000.]] Google ScholarDigital Library
- The ESTEREL language. {On-line} http://www.esterel.org.]]Google Scholar
- M. Gao and R. K. Brayton. Semi-algebraic methods for multi-valued logic. In Proc. of the Intl. Workshop on Logic Synthesis, May. 2000.]]Google Scholar
- M. Gao, J. Jiang, Y. Jiang, Y. Li, S. Singha, and R. K. Brayton. MVSIS. In Proc. of the Intl. Workshop on Logic Synthesis, May. 2001.]]Google Scholar
- O. Hainque, L. Pautet, Y. L. Biannic, and E. Nassor. Cronos: a separate compilation toolset for modular esterel applications. Formal Methods, 1999.]] Google ScholarDigital Library
- Y. Jiang and R. K. Brayton. Don't cares and multi-valued logic network minimization. In Proc. of the Intl. Conf. on Computer-Aided Design, Nov. 2000.]] Google ScholarDigital Library
- Y. Jiang and R. K. Brayton. Logic optimization and code generation for embedded control applications. In Proc. of the Intl. Symposium on Hardware/Software Co-Design, Apr. 2001.]] Google ScholarDigital Library
- C. Kim, L. Lavagno, and A. Sangiovanni-Vincentelli. Free MDD-based software optimization techniques for embedded systems. In Proc. of the Conf. on Design Automation & Test in Europe, Mar. 2000.]] Google ScholarDigital Library
- P. M. Maurer. Event driven simulation without loops or conditionals. In Proc. of the Intl. Conf. on Computer-Aided Design, Nov. 2001.]] Google ScholarDigital Library
- P. McGeer, K. McMillan, A. Saldanha, A. Sangiovanni-Vincentelli, and P. Scaglia. Fast discrete function evaluation using decision diagrams. In Proc. Of the Intl. Conf. on Computer-Aided Design, pages 402--407, Nov. 1995.]] Google ScholarDigital Library
- E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis. Technical Report UCB/ERL M92/41, Electronics Research Laboratory, Univ. of California, Berkeley, CA 94720, May 1992.]]Google Scholar
- E. M. Sentovich, H. Toma, and G. Berry. Latch optimization in circuits generated from high-level descriptions. In Proc. of the Intl. Conf. on Computer Aided Design, pages 428--35, Nov. 1996.]] Google ScholarDigital Library
- M. Sgrio, L. Lavagno, Y. Watanabe, and A. L. Sangiovanni-Vincentelli. Synthesis of embedded software using free-choice petri nets. In Proc. of the Design Automation Conf., June 1999.]] Google ScholarDigital Library
- R. Ubar, J. Raik, and A. Morawiec. Back-Tracing and Event-Driven Techniques in High-Level Simulation with Decision Diagrams. In Proc. of the Intl. Symposium on Circuits and Systems, pages 208--211, May 2000.]]Google ScholarCross Ref
- D. Weil, V. Bertin, E. Closse, M. Poize, P. Venier, and J. Pulou. Efficient compilation of Esterel for real-time embedded systems. In Proc. of the Intl. Conf. on Compilers, Architecture and Synthesis for Embedded Systems, Nov. 2000.]] Google ScholarDigital Library
Index Terms
- Software synthesis from synchronous specifications using logic simulation techniques
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