Jing-Jia Liou
ABSTRACT
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths.
- J.-J. Liou, A. Krstić, K.-T. Cheng, D. Mukherjee, and S. Kundu. Performance Sensitivity Analysis Using Statistical Methods and Its Applications to Delay Testing. Proc. ASP-DAC, pp 587--592, Jan 2000 Google Scholar
Digital Library
- J.-J. Liou, K.-T. Cheng, and D. Mukherjee. Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. Proc. of VTS, pp 97--104, Apr 2000 Google ScholarDigital Library
- J.-J. Liou, K.-T. Cheng, S. Kundu, and A. Krstic. Fast Statistical Timing Analysis by Probabilistic Event Propagation. Proc. of DAC, Jun 2001 Google ScholarDigital Library
- J.-J. Liou, A. Krstić, Y.-M. Jiang, and K.-T. Cheng. Path selection and pattern generation for dynamic timing analysis considering power supply noise effects. Proc. of ICCAD, pp 493--496, Nov 2000 Google ScholarDigital Library
- D. Brand and V. Iyengar. Timing Analysis Using Functional Analysis. IBM Thomas J. Watson Center, Technical Report, 1986Google Scholar
- P. McGeer and R. Brayton. Efficient Algorithms for Computing The Longest Viable Path in A Combinational Network. Proc. of DAC, pp 561--567, Jun 1989 Google ScholarDigital Library
- S. Devadas, K. Keutzer, and S. Malik. Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms. IEEE Trans. on CAD, 12(12):1913--1923, Dec 1993Google ScholarDigital Library
- H.-C. Chen and D. H. C. Du. Path Sensitization in Critical Path Problem. IEEE Trans. on CAD, 12(2):196--207, Feb 1993Google ScholarDigital Library
- H. Chang and J. A. Abraham. An Efficient Critical Path Tracing Algorithm for Designing High Performance VLSI Systems. JETTA, 11:119--129, 1997 Google ScholarDigital Library
- D. R. Tryon, F. M. Armstrong, and M. R. Reiter. Statistical Failure Analysis of System Timimg. IBM Journal of Research and Development, 28(4):340--355, Jul 1984 Google ScholarDigital Library
- H.-F. Jyu, S. Malik, S. Devadas, and K. Keutzer. Statistical Timing Analysis of Combinational Logic Circuits. IEEE Trans. on VLSI, 1(2):126--137, Jun 1993Google Scholar
- A. Krsti'c and K.-T. Cheng. Delay Fault Testing for VLSI Circuits. Kluwer Academic Publishers, Boston, MA, 1998Google Scholar
- W.-N. Li, S. M. Reddy, and S. K. Sahni. Long and Short Covering Edges in Combinational Logic Circuits. IEEE Trans. on CAD, 9(12):1245--1253, Dec 1990Google ScholarDigital Library
- S. Tani, M. Teramoto, T. Fukazawa, and K. Matsuhiro. Efficient Path Selection for Delay Testing Based on Partial Path Evaluation. Proc. of VTS, pp 188--193, May 1998 Google ScholarDigital Library
- H. Edamatsu, K. Homma, M. Kakimoto, Y. Koike, and K. Tabuchi. Pre-Layout Delay Calculation Specification for CMOS ASIC Libraries. Proc. of ASP-DAC, pp 241--248, Feb 1998Google ScholarCross Ref
- M. Sivaraman and A. J. Strojwas. Path delay fault diagnosis and coverage-a metric and an estimation technique. IEEE Trans. on CAD, 20(3):440--457, Mar 2001 Google ScholarDigital Library
- Anacad. Eldo v4.4.x User's Manual. 1996Google Scholar
Index Terms
- False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
Recommendations
An Efficient False Path-Aware Heuristic Critical Path Selection Method with High Coverage of the Process Variation Space
In this article, we present a critical path selection method that efficiently finds true (sensitizable) critical paths of a circuit in the presence of process variations. The method, which is based on the viability analysis, tries to select the least ...
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis
VTS '00: Proceedings of the 18th IEEE VLSI Test SymposiumVarious parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in nature can affect the performance of deep sub-micron designs. In order to capture the effects of these statistical variations on circuit ...
False path exclusion in delay analysis of RTL structures
In this paper, we present an accurate delay-estimation algorithm at the register-transfer level. We study three important sources of false paths in register-transfer-level (RTL) structures, i.e., 1) resource binding; 2) interdependent conditions; and 3) ...
Comments